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32 条记录 (耗时 0.033 秒)

    Method for forming a multi-layer metallic wiring structure
    21.
    发明授权
    Method for forming a multi-layer metallic wiring structure 失效
    用于形成多层金属布线结构的方法

    公开(公告)号：US5385867A

    公开(公告)日：1995-01-31

    申请号：US216968

    申请日：1994-03-24

    申请人： Tetsuya Ueda ,  Kousaku Yano ,  Tomoyasu Murakami ,  Michinari Yamanaka ,  Shuji Hirao ,  Noboru Nomura

    发明人： Tetsuya Ueda ,  Kousaku Yano ,  Tomoyasu Murakami ,  Michinari Yamanaka ,  Shuji Hirao ,  Noboru Nomura

    IPC分类号： H01L21/3205 ,  H01L21/768 ,  H01L23/522 ,  H01L21/283 ,  H01L21/31

    CPC分类号： H01L21/76847 ,  H01L21/76844 ,  H01L21/76877 ,  H01L21/76885 ,  H01L23/5226 ,  H01L2924/0002 ,  Y10S438/948

    摘要： After accumulating a BPSG film layer on a silicon substrate, a first Al--Si--Cu film layer, a W film layer and a second Al--Si--Cu film layer are successively accumulated on this BPSG film layer. A resist pattern with wide-width and narrow-width pattern portions is formed on the second Al--Si--Cu film layer. The wide-width pattern portion is provided at a position corresponding to a contact for connecting a first-layer metallic wiring and a second-layer metallic wiring, while the narrow-width pattern portion is provided at a position corresponding to a wiring portion for the first-layer metallic wiring. After applying first etching on the second Al--Si--Cu film layer with a mask of the resist patter, second etching is applied on the W film layer. Thereafter, by applying third etching, the resist pattern remaining on the first-layer metallic wiring is removed and the first Al--Si--Cu film layer is transfigured into a tall metallic film portion and a short metallic film portion. After accumulating an inter-layer insulating film layer on the first Al--Si--Cu film layer, etchback is applied on this inter-layer insulating film layer until the top of the tall metallic film portion is bared. Then, the second-layer metallic wiring is formed on the inter-layer insulating film layer so that the second-layer metallic wiring is connected with the tall metallic film portion.

    摘要翻译： 在硅衬底上积累BPSG膜层之后，第一Al-Si-Cu膜层，W膜层和第二Al-Si-Cu膜层依次堆积在该BPSG膜层上。 在第二Al-Si-Cu膜层上形成具有宽幅和窄宽图案部分的抗蚀剂图案。 宽幅图形部分设置在与用于连接第一层金属布线和第二层金属布线的接触件相对应的位置处，而窄宽图案部分设置在与布线部分相对应的位置处 第一层金属布线。 在具有抗蚀剂图案的掩模的第二Al-Si-Cu膜层上施加第一蚀刻之后，在W膜层上施加第二蚀刻。 此后，通过施加第三蚀刻，去除残留在第一层金属布线上的抗蚀剂图案，并将第一Al-Si-Cu膜层变形为高金属膜部分和短金属膜部分。 在第一Al-Si-Cu膜层上积累层间绝缘膜层之后，在该层间绝缘膜层上施加回蚀，直到高金属膜部分的顶部露出。 然后，在层间绝缘膜层上形成第二层金属布线，使得第二层金属布线与高金属膜部分连接。

    Stripe-color filter
    22.
    发明授权
    Stripe-color filter 失效
    条纹滤色片

    公开(公告)号：US4355866A

    公开(公告)日：1982-10-26

    申请号：US179875

    申请日：1980-08-20

    申请人： Eiichiro Tanaka ,  Kousaku Yano ,  Yoshitaka Aoki ,  Shinji Fujiwara

    发明人： Eiichiro Tanaka ,  Kousaku Yano ,  Yoshitaka Aoki ,  Shinji Fujiwara

    IPC分类号： G02B5/20 ,  H01J29/89 ,  G02B5/22 ,  G02B5/28

    CPC分类号： G02B5/201 ,  H01J29/898

    摘要： A stripe-color filter for spatial color encoding in a color TV camera, having a striped semiconductor filter-element-layer supported between a transparent substrate layer and a transparent dielectric covering layer. There are further provided a first coating layer of a transparent thin film between the substrate layer and the semiconductor filter-element-layer and a second coating layer of a transparent thin film between the semiconductor filter-element-layer and the covering layer. The refractive indexes of those layers are in the relationship: n.sub.F >n.sub.T1 >n.sub.S and n.sub.F >n.sub.T2 >n.sub.D, wherein n.sub.S represents the refractive index of the substrate layer, n.sub.T1 the first coating layer, n.sub.F the semiconductor filter-element-layer, n.sub.D the covering layer, and n.sub.T2 the second coating layer. Thus, the first and second coating layers act as anti-reflection layers, so that the spectral transmissivity at the semiconductor layer region of the stripe-color filter is improved.

    摘要翻译： 一种用于彩色电视摄像机中的空间颜色编码的条纹彩色滤光器，其具有支撑在透明基底层和透明电介质覆盖层之间的带状半导体滤光器元件层。 另外，在半导体滤光元件层与覆盖层之间，在基板层和半导体滤光元件层之间还设置透明薄膜的第一涂层和透明薄膜的第二涂层。 这些层的折射率为nF> nT1> nSandnF> nT2> nD，其中nS表示衬底层的折射率，nT1表示第一涂层，nF表示半导体滤光器元件层，nD表示 覆盖层，nT2为第二涂层。 因此，第一和第二涂层用作防反射层，从而提高条形滤色器半导体层区域的光谱透射率。

    Layer forming material and wiring forming method
    27.
    发明授权
    Layer forming material and wiring forming method 失效
    层形成材料和布线形成方法

    公开(公告)号：US06372928B1

    公开(公告)日：2002-04-16

    申请号：US09003826

    申请日：1998-01-07

    申请人： Akemi Kawaguchi ,  Yuka Terai ,  Kousaku Yano

    发明人： Akemi Kawaguchi ,  Yuka Terai ,  Kousaku Yano

    IPC分类号： C07F108

    CPC分类号： H01L21/32051 ,  C23C16/18 ,  H01L21/76838 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

    摘要： A layer forming material is a compound which has a structure of six-membered ring coordinated to Cu and containing Si, and of which general formula is represented by the following chemical formula: wherein X1 and X2 are elements of the VI group of the same or different types which are coordinate-bonded to Cu, and of which examples include O, S, Se, Te and the like, at least one of Y1, Y2 and Y3 is Si, L is a group which has a double or triple bond and which is able to supply electrons to Cu, and each of R1 and R2 is any of SiF3, SiH3, CF3 and CH3 for example.

    摘要翻译： 层形成材料是具有与Cu配位并含有Si的六元环结构的化合物，其通式由以下化学式表示：其中X1和X2是其VI基团的元素， 与Cu配位结合的不同类型，其实例包括O，S，Se，Te等，Y1，Y2和Y3中的至少一个为Si，L为具有双键或三键的基团， 其能够向Cu提供电子，并且R1和R2中的每一个例如是SiF 3，SiH 3，CF 3和CH 3中的任一种。

    Multi-layer wiring structure having varying-sized cutouts
    28.
    发明授权
    Multi-layer wiring structure having varying-sized cutouts 失效
    具有不同大小的切口的多层布线结构

    公开(公告)号：US5760429A

    公开(公告)日：1998-06-02

    申请号：US834303

    申请日：1997-02-18

    申请人： Kousaku Yano ,  Tetsuya Ueda

    发明人： Kousaku Yano ,  Tetsuya Ueda

    IPC分类号： H01L21/768 ,  H01L23/522 ,  H01L23/528

    CPC分类号： H01L23/5226 ,  H01L21/76805 ,  H01L2924/0002

    摘要： An integrated circuit having a multi-layered metal wiring structure with interlayer insulating films therebetween. A small cutout is made in a metal wiring when it is desirous to have the metal wiring touch a contact formed in a through hole passing through said cutout. A larger cutout is made in a metal wiring when it is desirous to have the metal wiring remain spaced from a contact formed in a through hole passing through said cutout.

    摘要翻译： 一种集成电路，具有在其间具有层间绝缘膜的多层金属布线结构。 当希望金属布线接触通过所述切口的通孔中形成的触点时，在金属布线中形成小切口。 当希望金属布线保持与通过所述切口的通孔中形成的触点间隔开时，在金属布线中形成较大的切口。

    Semiconductor device and associated fabrication method
    30.
    发明授权
    Semiconductor device and associated fabrication method 失效
    半导体器件及相关制造方法

    公开(公告)号：US5723909A

    公开(公告)日：1998-03-03

    申请号：US712237

    申请日：1996-09-11

    申请人： Kousaku Yano ,  Tatsuo Sugiyama ,  Satoshi Ueda ,  Noboru Nomura

    发明人： Kousaku Yano ,  Tatsuo Sugiyama ,  Satoshi Ueda ,  Noboru Nomura

    IPC分类号： H01L21/205 ,  H01L21/316 ,  H01L21/768 ,  H01L23/522 ,  H01L23/532 ,  H01L23/58

    CPC分类号： H01L23/5329 ,  H01L21/76801 ,  H01L21/76826 ,  H01L21/76832 ,  H01L21/76834 ,  H01L2924/0002

    摘要： A first metallization layer is locally formed on the surface of a semiconductor substrate thereby leaving portions of the semiconductor substrate's surface exposed. A first silicon oxide layer is then formed in such a manner that it covers the exposed portions of the semiconductor substrate's surface and the first metallization layer. This is followed by the formation of an HMDS molecular layer on the first silicon oxide layer. Then, a second silicon oxide is formed on the molecular layer by means of a CVD process utilizing the chemical reaction of ozone with TEOS. Finally, a second metallization layer is locally formed on the second silicon oxide layer.

    摘要翻译： 第一金属化层局部地形成在半导体衬底的表面上，从而使半导体衬底表面的部分露出。 然后以这样的方式形成第一氧化硅层，使得其覆盖半导体衬底的表面和第一金属化层的暴露部分。 随后在第一氧化硅层上形成HMDS分子层。 然后，通过使用臭氧与TEOS的化学反应的CVD工艺在分子层上形成第二氧化硅。 最后，第二金属化层局部形成在第二氧化硅层上。