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公开(公告)号：US07038969B2
公开(公告)日：2006-05-02
申请号：US10940635
申请日：2004-09-15
IPC分类号： G11C7/00
CPC分类号： G11C29/027 , G11C29/02
摘要： A semiconductor memory encompasses a memory cell array having a spare memory cell array; a holding circuit having banks of fuses, configured to read and hold fuse information; a decision circuit configured to determine which address of memory cell is to be replaced with which spare memory cell based on the fuse information from the holding circuit; and a holding-controller configured to control reading and holding of the fuse information in the holding circuit by receiving a power supply completion signal and a refresh signal. The holding circuit rereads the fuse information when the reread signal is generated, after the holding circuit reads once the fuse information by receiving the power supplying completion signal.
摘要翻译： 半导体存储器包括具有备用存储单元阵列的存储单元阵列; 具有保险丝组的保持电路，被配置为读取和保持熔丝信息; 判定电路，被配置为基于来自保持电路的熔丝信息来确定存储器单元的哪个地址将被替换为哪个备用存储器单元; 以及保持控制器，被配置为通过接收电源完成信号和刷新信号来控制保持电路中的熔丝信息的读取和保持。 当保持电路通过接收供电完成信号一次读取熔丝信息之后，保持电路在产生再读信号时重新读取熔丝信息。
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公开(公告)号：US07035153B2
公开(公告)日：2006-04-25
申请号：US10978457
申请日：2004-11-02
IPC分类号： G11C29/00
CPC分类号： G11C29/816 , G11C7/1048 , G11C7/18 , G11C11/4097
摘要： A semiconductor memory device adopting a bit line twist system in which at least a part of bit lines are twisted, includes memory cell arrays each having a plurality of memory cells to store data, redundancy cell arrays each having a plurality of redundancy cells to replace a defective cell in the memory cell array, and a control circuit which performs control to invert a direction of the data. The device further includes an inversion circuit which inverts the direction of the data, in accordance with the control by the control circuit.
摘要翻译： 采用位线扭转系统的半导体存储器件，其中位线的至少一部分被扭曲，包括每个具有多个存储单元以存储数据的存储单元阵列，每个具有多个冗余单元的冗余单元阵列以替代 存储单元阵列中的有缺陷的单元，以及执行用于反转数据的方向的控制的控制电路。 该装置还包括根据控制电路的控制来反转数据的方向的反相电路。
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公开(公告)号：US20050088874A1
公开(公告)日：2005-04-28
申请号：US10940635
申请日：2004-09-15
IPC分类号： G11C11/413 , G11C29/02 , G11C29/04 , G11C17/00
CPC分类号： G11C29/027 , G11C29/02
摘要： A semiconductor memory encompasses a memory cell array having a spare memory cell array; a holding circuit having banks of fuses, configured to read and hold fuse information; a decision circuit configured to determine which address of memory cell is to be replaced with which spare memory cell based on the fuse information from the holding circuit; and a holding-controller configured to control reading and holding of the fuse information in the holding circuit by receiving a power supply completion signal and a refresh signal. The holding circuit rereads the fuse information when the reread signal is generated, after the holding circuit reads once the fuse information by receiving the power supplying completion signal.
摘要翻译： 半导体存储器包括具有备用存储单元阵列的存储单元阵列; 具有保险丝组的保持电路，被配置为读取和保持熔丝信息; 判定电路，被配置为基于来自保持电路的熔丝信息来确定存储器单元的哪个地址将被替换为哪个备用存储器单元; 以及保持控制器，被配置为通过接收电源完成信号和刷新信号来控制保持电路中的熔丝信息的读取和保持。 当保持电路通过接收供电完成信号一次读取熔丝信息之后，保持电路在产生再读信号时重新读取熔丝信息。
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24.发明授权Semiconductor integrated circuit having clock synchronous type circuit and clock non-synchronous type circuit 失效具有时钟同步型电路和时钟非同步型电路的半导体集成电路公开(公告)号：US06839859B2
公开(公告)日：2005-01-04
申请号：US09966667
申请日：2001-09-27
IPC分类号： G11C11/413 , G06F12/00 , G11C7/10 , G11C7/22 , G11C8/18 , G11C11/407 , G06F13/42
CPC分类号： G11C7/1072 , G11C7/1045 , G11C7/22 , G11C2207/2281
摘要： A clock non-synchronous type circuit performs data read operation on the basis of a read control signal. After a lapse of a predetermined delay time, read data is read out from the clock non-synchronous type circuit. The read data is latched in selected one of N latch circuits. A latch circuit is selected on the basis of a control signal instead of a clock signal. The control signal represents that read data is output from the clock non-synchronous type circuit, and hence a latch circuit is always selected after read data is output.
摘要翻译： 时钟非同步型电路基于读取控制信号执行数据读取操作。 在经过预定的延迟时间之后，从时钟非同步型电路中读出读数据。 读取的数据被锁存在N个锁存电路中的选定的一个中。 基于控制信号而不是时钟信号来选择锁存电路。 控制信号表示从时钟非同步型电路输出读取数据，因此在读出数据输出后始终选择锁存电路。
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公开(公告)号：US4592410A
公开(公告)日：1986-06-03
申请号：US663561
申请日：1984-10-22
申请人： Tsutomu Takamoto , Yasutake Ohhashi , Hisao Nishimura , Yutaka Hirata , Takashi Okazaki , Masahiro Yoshihara
发明人： Tsutomu Takamoto , Yasutake Ohhashi , Hisao Nishimura , Yutaka Hirata , Takashi Okazaki , Masahiro Yoshihara
CPC分类号： B22D11/204 , B22D11/203
摘要： A process for continuously casting thin slabs, which comprises the steps of pouring a molten metal from a large-sized tundish through a sliding nozzle into a small-sized tundish, over-flowing the molten metal from the small-sized tundish to pour the molten metal into a continuous casting machine of the twin-belt type is disclosed. According to the process, a pouring rate into the small-sized tundish is calculated prior to overflow on the basis of a change in weight of the small-sized tundish and the degree of opening of the sliding nozzle is adjusted so as to make the calculated pouring rate come close to the target pouring rate into the small-sized tundish or into the casting machine.
摘要翻译： 一种用于连续铸造薄板坯的方法，其包括以下步骤：将来自大型中间包的熔融金属通过滑动喷嘴浇注到小型中间包中，使来自小型中间包的熔融金属过度流动以将熔融的 公开了将金属制成双带式连续铸造机。 根据该过程，基于小型中间包的重量变化，在溢出之前计算向小型中间包的倾倒率，并且调节滑动喷嘴的开度以使得计算出的 浇注速率接近目标浇注速率进入小型中间包或铸造机。
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公开(公告)号：US08797807B2
公开(公告)日：2014-08-05
申请号：US13432708
申请日：2012-03-28
申请人： Masahiro Yoshihara , Katsumi Abe
发明人： Masahiro Yoshihara , Katsumi Abe
CPC分类号： G11C7/1078 , G11C7/08 , G11C7/1051 , G11C7/106 , G11C7/1087 , G11C7/12 , G11C7/22 , G11C16/0483 , G11C16/10 , G11C16/26 , G11C16/3418 , G11C2207/2227 , G11C2207/2245
摘要： According to one embodiment, the semiconductor memory includes a memory cell array which includes memory cells to store data, a buffer circuit which includes latches, each of the latches including transistors as control elements and a flip-flop, and a control circuit which turns off the transistors to deactivate one or more of the latches.
摘要翻译： 根据一个实施例，半导体存储器包括存储单元阵列，其包括用于存储数据的存储单元，包括锁存器的缓冲电路，每个锁存器包括作为控制元件的晶体管和触发器，以及控制电路， 晶体管去激活一个或多个锁存器。
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公开(公告)号：US08559226B2
公开(公告)日：2013-10-15
申请号：US13052148
申请日：2011-03-21
IPC分类号： G11C16/04
CPC分类号： G11C16/26 , G11C11/5642 , G11C16/12 , G11C16/32 , G11C16/3468
摘要： According to one embodiment, a threshold detecting method for detecting threshold values of nonvolatile semiconductor memory cells comprises applying a preset voltage to a word line connected to the memory cells, and performing bit-line sense at two different timings during discharging of one of a bit line connected to the memory cells and a node corresponding to the bit line, while a potential of the word line is kept constant.
摘要翻译： 根据一个实施例，用于检测非易失性半导体存储单元的阈值的阈值检测方法包括：将预设电压施加到连接到存储单元的字线，以及在放电期间的两个不同定时执行位线检测 线连接到存储器单元和对应于位线的节点，而字线的电位保持恒定。
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公开(公告)号：US20110305089A1
公开(公告)日：2011-12-15
申请号：US13052148
申请日：2011-03-21
CPC分类号： G11C16/26 , G11C11/5642 , G11C16/12 , G11C16/32 , G11C16/3468
摘要： According to one embodiment, a threshold detecting method for detecting threshold values of nonvolatile semiconductor memory cells comprises applying a preset voltage to a word line connected to the memory cells, and performing bit-line sense at two different timings during discharging of one of a bit line connected to the memory cells and a node corresponding to the bit line, while a potential of the word line is kept constant.
摘要翻译： 根据一个实施例，用于检测非易失性半导体存储单元的阈值的阈值检测方法包括：将预设电压施加到连接到存储单元的字线，以及在放电期间的两个不同定时执行位线检测 线连接到存储器单元和对应于位线的节点，而字线的电位保持恒定。
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公开(公告)号：US07839679B2
公开(公告)日：2010-11-23
申请号：US12043510
申请日：2008-03-06
申请人： Koji Hosono , Masahiro Yoshihara , Dai Nakamura , Youichi Kai
发明人： Koji Hosono , Masahiro Yoshihara , Dai Nakamura , Youichi Kai
CPC分类号： G11C16/30 , G11C5/14 , H01L2924/0002 , H01L2924/00
摘要： A nonvolatile semiconductor memory according to an aspect of the invention includes memory cell arrays including plural cell units, a power supply pad disposed on one end in a first direction of the memory cell arrays, and page buffers disposed in the first direction of the memory cell arrays. The nonvolatile semiconductor memory also includes plural bit lines which are disposed on the memory cell arrays while extending in the first direction and a first power supply line which is disposed on the plural bit lines on the memory cell arrays to connect the power supply pad and the page buffers.
摘要翻译： 根据本发明的一个方面的非易失性半导体存储器包括存储单元阵列，其包括多个单元单元，设置在存储单元阵列的第一方向上的一端的电源垫，以及设置在存储单元的第一方向上的页缓冲器 阵列 非易失性半导体存储器还包括多个位线，它们沿着第一方向延伸设置在存储单元阵列上，第一电源线设置在存储单元阵列上的多个位线上，以将电源焊盘和 页面缓冲区。
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30.发明授权Semiconductor device having auto trimming function for automatically adjusting voltage 失效具有自动修整功能的半导体器件，用于自动调节电压公开(公告)号：US07359255B2
公开(公告)日：2008-04-15
申请号：US11438345
申请日：2006-05-23
IPC分类号： G11C7/00
CPC分类号： H03M1/1061 , G11C5/147 , G11C16/30 , G11C29/02 , G11C29/021 , G11C29/028
摘要： A reference voltage generation circuit generates a reference voltage. An internal voltage generation circuit generates an internal voltage on the basis of the reference voltage generated by the reference voltage generation circuit. A first trimming circuit trims the internal voltage. During trimming of the internal voltage, the first trimming circuit trims an externally supplied first target voltage in accordance with first trimming data. The first trimming circuit ends the trimming when the first target voltage meets a given condition for the reference voltage.
摘要翻译： 参考电压产生电路产生参考电压。 内部电压产生电路基于由参考电压产生电路产生的参考电压产生内部电压。 第一个微调电路修剪内部电压。 在微调内部电压期间，第一微调电路根据第一微调数据修正外部提供的第一目标电压。 当第一目标电压满足参考电压的给定条件时，第一微调电路结束修整。
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