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公开(公告)号：US20070109870A1
公开(公告)日：2007-05-17
申请号：US11652023
申请日：2007-01-11
IPC分类号： G11C16/04
CPC分类号： H01L27/11521 , G11C16/0425 , G11C16/0433 , G11C16/12 , G11C16/3459 , H01L27/115 , H01L27/11524
摘要： Suppressing a leakage current is required in a flash memory because the channel length is made shorter with a reduction in the memory cell size. In an AND type memory array having an assist electrode, although the memory cell area has been reduced by the field isolation using a MOS transistor, leakage current in the channel direction becomes greater with a reduction in the memory cell size, resulting in problems arising like deterioration of programming characteristics, an increase in the current consumption, and reading failure. To achieve the objective, in the present invention, electrical isolation is performed by controlling at least one assist electrode of the assist electrodes wired in parallel to be a negative voltage during program and read operations and by making the semiconductor substrate surface in the vicinity of the aforementioned assist electrode non-conductive.
摘要翻译： 在闪速存储器中需要抑制泄漏电流，因为随着存储器单元尺寸的减小，通道长度变短。 在具有辅助电极的AND型存储器阵列中，虽然通过使用MOS晶体管的场隔离来减小存储单元面积，但是由于存储单元尺寸的减小，沟道方向的泄漏电流变大，导致出现像 编程特性恶化，电流消耗增加，读取失败。 为了实现该目的，在本发明中，通过在编程和读取操作期间将辅助电极并联布置的至少一个辅助电极作为负电压进行电隔离，并且通过使半导体衬底表面在 上述辅助电极不导电。
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公开(公告)号：US07190017B2
公开(公告)日：2007-03-13
申请号：US11022773
申请日：2004-12-28
IPC分类号： H01L29/76
CPC分类号： H01L27/11526 , G11C16/0491 , H01L27/115 , H01L27/11521 , H01L27/11531
摘要： Reliability of a semiconductor device having a nonvolatile memory comprising first through third gate electrodes is enhanced. With a flash memory having first gate electrodes (floating gate electrodes), second gate electrodes (control gate electrodes) and third gate electrodes, isolation parts are formed in a self-aligned manner against patterns of a conductor film for forming the third gate electrodes by filling up the respective isolation grooves and a gate insulator film for select nMISes in a peripheral circuit region is formed prior to the formation of the isolation parts. By so doing, deficiency with the gate insulator film for the select nMISes, caused by stress occurring to the isolation parts, can be reduced. Further, with the semiconductor device including the case of stacked memory cells, the patterns of the conductor film for forming the third gate electrodes, serving as a mask for forming the isolation parts in the self-aligned manner, can be formed without misalignment against channels.
摘要翻译： 具有包括第一至第三栅电极的非易失性存储器的半导体器件的可靠性得到增强。 利用具有第一栅电极（浮栅电极），第二栅电极（控制栅电极）和第三栅电极的闪速存储器，隔离部分以自对准的方式形成，以抵抗用于形成第三栅电极的导体膜的图案 填充相应的隔离沟槽，并且在形成隔离部件之前形成用于在外围电路区域中选择的nMIS的栅极绝缘膜。 通过这样做，可以减少由隔离部分发生的应力引起的用于选择性nMIS的栅极绝缘膜的缺陷。 此外，通过包括堆叠的存储单元的情况的半导体器件，可以形成用作形成隔离部件的自对准方式的掩模的用于形成第三栅电极的导体膜的图案，而不对准通道 。
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公开(公告)号：US07184318B2
公开(公告)日：2007-02-27
申请号：US11197485
申请日：2005-08-05
CPC分类号： H01L27/11521 , G11C16/0425 , G11C16/0433 , G11C16/12 , G11C16/3459 , H01L27/115 , H01L27/11524
摘要： Suppressing a leakage current is required in a flash memory because the channel length is made shorter with a reduction in the memory cell size. In an AND type memory array having an assist electrode, although the memory cell area has been reduced by the field isolation using a MOS transistor, leakage current in the channel direction becomes greater with a reduction in the memory cell size, resulting in problems arising like deterioration of programming characteristics, an increase in the current consumption, and reading failure. To achieve the objective, in the present invention, electrical isolation is performed by controlling at least one assist electrode of the assist electrodes wired in parallel to be a negative voltage during program and read operations and by making the semiconductor substrate surface in the vicinity of the aforementioned assist electrode non-conductive.
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公开(公告)号：US20060171207A1
公开(公告)日：2006-08-03
申请号：US11340686
申请日：2006-01-27
IPC分类号： G11C16/04
CPC分类号： G11C16/0491 , G11C16/0433 , H01L21/28273 , H01L27/115 , H01L27/11521 , H01L27/11524 , H01L29/42328 , H01L29/66825 , H01L29/7881
摘要： The programming speed of a nonvolatile semiconductor memory device used as a flash memory is increased as follows. First, second, and third assist gates, a control gate, as well as first and second storage nodes are created over a p-type well. In the course of a programming operation, first of all, the p-type well is set at 0V. Then, a first inversion layer created by setting the first assist gate at a voltage A is set at a voltage B and the second assist gate is set at a voltage C. Subsequently, a second inversion layer created by setting the third assist gate at a voltage D is set at a voltage E and the control gate is set at a voltage F to inject hot electrons generated on the surface of the p-type well in close proximity to the second assist gate into the second storage node.
摘要翻译： 用作闪存的非易失性半导体存储器件的编程速度增加如下。 第一，第二和第三辅助门，在p型阱上创建控制栅极以及第一和第二存储节点。 在编程操作过程中，首先将p型阱置于0V。 然后，将通过将第一辅助栅极设置为电压A而形成的第一反转层设定为电压B，将第二辅助栅设定为电压C.接着，将第三辅助栅设定为a 电压D设定为电压E，控制栅极被设定为电压F，以将在p型阱的表面上产生的热电子注入紧邻第二辅助栅极的第二存储节点。
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25.发明申请公开(公告)号：US20060001081A1
公开(公告)日：2006-01-05
申请号：US11166114
申请日：2005-06-27
IPC分类号： H01L29/788
CPC分类号： H01L27/115 , G11C16/0433 , G11C16/0491 , H01L27/11521
摘要： A leakage current flowing between data lines of a nonvolatile semiconductor memory is reduced. In a memory array of a nonvolatile semiconductor memory device having an AND type flash memory, a concave portion is formed in a junction isolation area between adjacent word limes and between adjacent assist gate wirings AGL, and the height of a main surface (first main surface) of a semiconductor substrate in the region where the concave portion is formed is made lower than that of the main surface (second main surface) of the semiconductor substrate to which an assist gate wiring is facing. As a result, it is possible to control the leakage current that flows between the drain line and source line in the aforementioned junction isolation region during operation of a flash memory.
摘要翻译： 在非易失性半导体存储器的数据线之间流动的漏电流减少。 在具有AND型闪速存储器的非易失性半导体存储器件的存储器阵列中，在相邻字灰度之间和相邻辅助栅极布线AGL之间的结隔离区域中形成凹部，并且在主表面（第一主表面 ）形成在形成有凹部的区域中的半导体衬底的低于辅助栅极布线所面对的半导体衬底的主表面（第二主表面）的厚度。 结果，可以在闪速存储器的操作期间控制在上述结隔离区域中的漏极线和源极线之间流动的漏电流。
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公开(公告)号：US20050151168A1
公开(公告)日：2005-07-14
申请号：US11022773
申请日：2004-12-28
IPC分类号： H01L21/8234 , G11C16/04 , H01L21/8247 , H01L27/088 , H01L27/10 , H01L27/115 , H01L29/788 , H01L29/792 , H01L29/73 , H01L21/82
CPC分类号： H01L27/11526 , G11C16/0491 , H01L27/115 , H01L27/11521 , H01L27/11531
摘要： Reliability of a semiconductor device having a nonvolatile memory comprising first through third gate electrodes is enhanced. With a flash memory having first gate electrodes (floating gate electrodes), second gate electrodes (control gate electrodes) and third gate electrodes, isolation parts are formed in a self-aligned manner against patterns of a conductor film for forming the third gate electrodes by filling up the respective isolation grooves and a gate insulator film for select nMISes in a peripheral circuit region is formed prior to the formation of the isolation parts. By so doing, deficiency with the gate insulator film for the select nMISes, caused by stress occurring to the isolation parts, can be reduced. Further, with the semiconductor device including the case of stacked memory cells, the patterns of the conductor film for forming the third gate electrodes, serving as a mask for forming the isolation parts in the self-aligned manner, can be formed without misalignment against channels.
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公开(公告)号：US09293508B2
公开(公告)日：2016-03-22
申请号：US14349386
申请日：2011-10-07
CPC分类号： H01L27/2481 , H01L27/2409 , H01L27/2454 , H01L45/06 , H01L45/1226 , H01L45/1233 , H01L45/124 , H01L45/144 , H01L45/1683
摘要： A memory cell array having such a structure that can be realized with a simpler process and ideal for realizing a higher density is provided. Memory cells have a structure in which channel layers (88p and 89p) are formed on the side surfaces of each of a plurality of stacked structures which extends in the Y direction and is periodically formed in the X direction with a gate insulator film layer (9) interposed, and a resistance-change material layer (7) is formed so as to be electrically connected to two adjacent channel layers of the channel layers. Due to such a structure, it is not necessary to perform such a very difficult step that processes the resistance-change material and the silicons collectively and it is possible to provide the memory cell array with a simpler process.
摘要翻译： 提供具有能够以更简单的处理实现并且实现更高密度的理想的具有这种结构的存储单元阵列。 存储单元具有这样的结构，其中沟道层（88p和89p）形成在多个层叠结构中的每一个在Y方向上延伸并且沿X方向周期性地形成的栅极绝缘膜层（9 ），并且形成电阻变化材料层（7），以电连接到沟道层的两个相邻沟道层。 由于这样的结构，不需要进行这样一个非常困难的步骤，即整体地处理电阻变化材料和硅，并且可以以更简单的工艺来提供存储单元阵列。
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公开(公告)号：US08730717B2
公开(公告)日：2014-05-20
申请号：US13104005
申请日：2011-05-09
申请人： Satoru Hanzawa , Yoshitaka Sasago
发明人： Satoru Hanzawa , Yoshitaka Sasago
IPC分类号： G11C11/00
CPC分类号： G11C13/003 , G11C13/0004 , G11C13/0026 , G11C13/0028 , G11C2213/71 , G11C2213/72 , G11C2213/75 , G11C2213/78 , H01L27/2454 , H01L27/2472 , H01L27/2481 , H01L45/06 , H01L45/124 , H01L45/144
摘要： A semiconductor device has multiple memory cell groups arranged at intersections between multiple word lines and multiple bit lines intersecting the word lines. The memory cell groups each have first and second memory cells connected in series. Each of the first and the second memory cells has a select transistor and a resistive storage device connected in parallel. The gate electrode of the select transistor in the first memory cell is connected with a first gate line, and the gate electrode of the select transistor in the second memory cell is connected to a second gate line. A first circuit block for driving the word lines (word driver group WDBK) is arranged between a second circuit block for driving the first and second gate lines (phase-change-type chain cell control circuit PCCCTL) and multiple memory cell groups (memory cell array MA).
摘要翻译： 半导体器件具有布置在多个字线和与字线相交的多个位线之间的交叉处的多个存储单元组。 存储单元组各自具有串联连接的第一和第二存储器单元。 第一和第二存储单元中的每一个具有并联连接的选择晶体管和电阻存储器件。 第一存储单元中的选择晶体管的栅电极与第一栅极线连接，第二存储单元中的选择晶体管的栅电极连接到第二栅极线。 用于驱动字线的第一电路块（字驱动器组WDBK）被布置在用于驱动第一和第二栅极线（相变型链单元控制电路PCCCTL）的第二电路块和多个存储单元组 阵列MA）。
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公开(公告)号：US08699262B2
公开(公告)日：2014-04-15
申请号：US13270299
申请日：2011-10-11
申请人： Takao Watanabe , Satoru Hanzawa , Yoshitaka Sasago
发明人： Takao Watanabe , Satoru Hanzawa , Yoshitaka Sasago
IPC分类号： G11C11/24
CPC分类号： H01L45/06 , G11C13/0004 , G11C13/003 , G11C13/0069 , G11C2213/71 , G11C2213/72 , G11C2213/75 , G11C2213/78 , G11C2213/79 , H01L27/2481
摘要： Adverse effects of a parasitic resistance and a parasitic capacitance of a driver circuit to a memory cell causes problems of thermal disturbance to a not-selected cell, unevenness of application voltage, degradation of a memory element in reading. A capacitor (C) is provided above or beneath a memory cell (MC) that includes a memory element to which a current write memory information and a selection element connected to the memory element. A charge stored in this capacitor writes to the memory element.
摘要翻译： 驱动电路的寄生电阻和寄生电容对存储单元的不利影响引起对未选择单元的热扰动，施加电压的不均匀性，读取中存储元件的劣化的问题。 电容器（C）设置在存储单元（MC）的上方或下方，存储单元（MC）包括与存储元件连接的当前写入存储器信息和选择元件的存储元件。 存储在该电容器中的电荷写入存储器元件。
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公开(公告)号：US20120087178A1
公开(公告)日：2012-04-12
申请号：US13270299
申请日：2011-10-11
申请人： Takao WATANABE , Satoru Hanzawa , Yoshitaka Sasago
发明人： Takao WATANABE , Satoru Hanzawa , Yoshitaka Sasago
IPC分类号： G11C11/24
CPC分类号： H01L45/06 , G11C13/0004 , G11C13/003 , G11C13/0069 , G11C2213/71 , G11C2213/72 , G11C2213/75 , G11C2213/78 , G11C2213/79 , H01L27/2481
摘要： Adverse effects of a parasitic resistance and a parasitic capacitance of a driver circuit to a memory cell causes problems of thermal disturbance to a not-selected cell, unevenness of application voltage, degradation of a memory element in reading. A capacitor (C) is provided above or beneath a memory cell (MC) that includes a memory element to which a current write memory information and a selection element connected to the memory element. A charge stored in this capacitor writes to the memory element.
摘要翻译： 驱动电路的寄生电阻和寄生电容对存储单元的不利影响引起对未选择单元的热扰动，施加电压的不均匀性，读取中存储元件的劣化的问题。 电容器（C）设置在存储单元（MC）的上方或下方，存储单元（MC）包括与存储元件连接的当前写入存储器信息和选择元件的存储元件。 存储在该电容器中的电荷写入存储器元件。
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