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    Semiconductor integrated circuit device
    26.
    发明授权
    Semiconductor integrated circuit device 有权

    公开(公告)号：US07612417B2

    公开(公告)日：2009-11-03

    申请号：US11042172

    申请日：2005-01-26

    申请人： Kenichi Osada ,  Masataka Minami ,  Shuji Ikeda ,  Koichiro Ishibashi

    发明人： Kenichi Osada ,  Masataka Minami ,  Shuji Ikeda ,  Koichiro Ishibashi

    IPC分类号： H01L29/76 ,  H01L27/11

    CPC分类号： H01L27/1104 ,  G11C11/412 ,  G11C11/417 ,  H01L27/11 ,  H01L29/4916 ,  H01L29/783 ,  Y10S257/904

    摘要： Prior known static random access memory (SRAM) cells are required that a diffusion layer be bent into a key-like shape in order to make electrical contact with a substrate with a P-type well region formed therein, which would result in a decrease in asymmetry leading to occurrence of a problem as to the difficulty in micro-patterning. To avoid this problem, the P-type well region in which an inverter making up an SRAM cell is formed is subdivided into two portions, which are disposed on the opposite sides of an N-type well region NW1 and are formed so that a diffusion layer forming a transistor has no curvature while causing the layout direction to run in a direction parallel to well boundary lines and bit lines. At intermediate locations of an array, regions for use in supplying power to the substrate are formed in parallel to word lines in such a manner that one regions is provided per group of thirty two memory cell rows or sixty four cell rows.

    Semiconductor memory device with memory cells operated by boosted voltage
    29.
    发明授权
    Semiconductor memory device with memory cells operated by boosted voltage 有权
    具有由升压电压工作的存储单元的半导体存储器件

    公开(公告)号：US07397693B2

    公开(公告)日：2008-07-08

    申请号：US11657026

    申请日：2007-01-24

    申请人： Masanao Yamaoka ,  Kenichi Osada ,  Koichiro Ishibashi

    发明人： Masanao Yamaoka ,  Kenichi Osada ,  Koichiro Ishibashi

    IPC分类号： G11C11/00

    CPC分类号： G11C11/417 ,  G11C11/412 ,  Y10S257/903

    摘要： A memory using an SRAM memory cell intended for low-voltage operation is designed to decrease the threshold value of MOS transistors constituting the memory cell without substantial decrease in the static noise margin, which is the operational margin of the memory cell. To this end, a voltage Vdd′ higher than a power supply voltage Vdd of a power supply line for peripheral circuits is supplied from a power supply line for memory cells as a power supply voltage for memory cells. Since the conductance of driver MOS transistors is in-creased, the threshold voltage of the MOS transistors within the memory cells can be reduced without reducing the static noise margin. Further the ratio of width between the driver MOS transistor and a transfer MOS transistor can be set to 1, thereby allowing a reduction in the memory cell area.

    摘要翻译： 使用用于低电压操作的SRAM存储单元的存储器被设计为降低构成存储器单元的MOS晶体管的阈值，而不会显着降低静态噪声容限，这是存储单元的操作余量。 为此，作为存储单元的电源电压，从用于存储单元的电源线提供高于外围电路用电源线的电源电压Vdd的电压Vdd'。 由于驱动器MOS晶体管的电导被增加，所以可以在不降低静态噪声容限的情况下减小存储单元内的MOS晶体管的阈值电压。 此外，可以将驱动器MOS晶体管和转移MOS晶体管之间的宽度比设置为1，从而允许存储单元区域的减小。

    SEMICONDUCTOR INTEGRATED CIRCUIT AND MANUFACTURING METHOD THEREFOR
    30.
    发明申请
    SEMICONDUCTOR INTEGRATED CIRCUIT AND MANUFACTURING METHOD THEREFOR 审中-公开
    半导体集成电路及其制造方法

    公开(公告)号：US20080143423A1

    公开(公告)日：2008-06-19

    申请号：US11943095

    申请日：2007-11-20

    申请人： Shigenobu Komatsu ,  Kenichi Osada ,  Masanao Yamaoka ,  Koichiro Ishibashi

    发明人： Shigenobu Komatsu ,  Kenichi Osada ,  Masanao Yamaoka ,  Koichiro Ishibashi

    IPC分类号： H03K3/01 ,  H01L21/8238

    CPC分类号： H01L27/092 ,  H01L21/823878 ,  H01L21/823892 ,  H01L27/1203 ,  H03K19/0027 ,  H03K19/00315

    摘要： The present invention is directed to realize high manufacture yield and compensate variations in threshold voltage of a MOS transistor with small overhead. A semiconductor integrated circuit includes a CMOS circuit for processing an input signal in an active mode, a control switch, and a control memory. The control switch supplies a pMOS body bias voltage and an nMOS body bias voltage to an N well in a pMOS transistor and a P well in an nMOS transistor, respectively, in the CMOS circuit. The control memory stores control information indicating whether or not the pMOS body bias voltage and the nMOS body bias voltage are supplied from the control switch to the N well in the pMOS transistor and the P well in the nMOS transistor, respectively, in the CMOS circuit in the active mode.

    摘要翻译： 本发明旨在实现高制造成品率并补偿具有较小开销的MOS晶体管的阈值电压的变化。 半导体集成电路包括用于处理活动模式中的输入信号的CMOS电路，控制开关和控制存储器。 控制开关分别向CMOS电路中的nMOS晶体管中的pMOS晶体管和P阱中的N阱施加pMOS体偏置电压和nMOS体偏置电压。 控制存储器存储指示pMOS体偏置电压和nMOS体偏置电压是否从控制开关提供到CMOS电路中的nMOS晶体管中的pMOS晶体管和P阱中的N阱的控制信息 处于活动模式。