公开(公告)号：US20120133540A1

公开(公告)日：2012-05-31

申请号：US13284822

申请日：2011-10-28

申请人： Seong Hoon CHOI ,  Jang Hyun Park ,  Chang Sun Kim ,  Jihun Eo ,  Young-Chan Jang

发明人： Seong Hoon CHOI ,  Jang Hyun Park ,  Chang Sun Kim ,  Jihun Eo ,  Young-Chan Jang

IPC分类号： H03M1/50

CPC分类号： H03M1/50 ,  H03M1/46

摘要： Provided is a time-domain voltage comparator including a voltage-time converter. The voltage-time converter includes a conversion unit and an output unit. The conversion unit includes a first MOS transistor which shifts a voltage level of the first detection node according to an external first voltage signal, and a second MOS transistor which shifts a voltage level of the second detection node according to an external second voltage signal. The output unit generates first and second output signals in response to voltages of the first and second detection nodes. The output unit determines a shifted time of the first output signal according to a voltage level of the first detection node and determines a shifted time of the second output signal according to a voltage level of the second detection node.

摘要翻译： 提供了包括电压 - 时间转换器的时域电压比较器。 电压 - 时间转换器包括转换单元和输出单元。 转换单元包括：第一MOS晶体管，其根据外部第一电压信号偏移第一检测节点的电压电平;以及第二MOS晶体管，其根据外部第二电压信号偏移第二检测节点的电压电平。 输出单元响应于第一和第二检测节点的电压产生第一和第二输出信号。 输出单元根据第一检测节点的电压电平确定第一输出信号的移位时间，并根据第二检测节点的电压电平确定第二输出信号的移位时间。

公开(公告)号：US08103917B2

公开(公告)日：2012-01-24

申请号：US12592271

申请日：2009-11-20

申请人： Young-Chan Jang

发明人： Young-Chan Jang

IPC分类号： G11B20/20 ,  G11C29/00

CPC分类号： G11C29/02 ,  G11C29/022 ,  G11C29/023 ,  G11C29/028

摘要： In a circuit and method for correcting skew among a plurality of communication channels used in communicating with a memory circuit, and in a memory controller and memory controlling method, and in a memory system and method, the circuit for correcting skew includes a transmitting circuit for transmitting a reference signal to input ends of the plurality of channels and through the plurality of channels, and a plurality of receiving circuits for receiving at the input ends of the plurality of channels a respective plurality of reflected signals, the reflected signals being reflected from respective output ends of the plurality of channels. A detection circuit receives the reflected signals and detects relative signal propagation time differences between the plurality of channels. A delay circuit coupled to at least one of the channels sets a signal propagation delay in the at least one of the channels based on the detected relative signal propagation time differences.

摘要翻译： 在用于与存储器电路通信使用的多个通信信道中的偏差校正的电路和方法中，以及在存储器控制器和存储器控制方法中，并且在存储器系统和方法中，用于校正偏斜的电路包括用于 将参考信号发送到多个信道的输入端并通过多个信道，以及多个接收电路，用于在多个信道的输入端接收相应的多个反射信号，反射信号从相应的多个信道反射 输出多个通道的端部。 检测电路接收反射信号并检测多个通道之间的相对信号传播时间差。 耦合到至少一个通道的延迟电路基于检测到的相对信号传播时间差设置至少一个信道中的信号传播延迟。

公开(公告)号：US08023608B2

公开(公告)日：2011-09-20

申请号：US12121017

申请日：2008-05-15

申请人： Young-Chan Jang

发明人： Young-Chan Jang

IPC分类号： H03D3/24

CPC分类号： G11C7/1051 ,  G11C7/106 ,  G11C7/1066 ,  G11C7/1078 ,  G11C7/1087 ,  G11C7/1093 ,  H04L7/0008 ,  H04L7/033

摘要： A communication system using multi-phase clock signals. The communication system includes a transmitter and a receiver. The transmitter outputs first data and a clock signal based on first multi-phase clock signals, and performs a coarse lock operation on the clock signal in response to a bit lock detection signal indicating whether or not the first data are bit-locked. The receiver receives the first data and the clock signal from the transmitter, generates second multi-phase clock signals based on the clock signal, generates second data by sampling the first data based on the second multi-phase clock signals, and performs a fine lock operation on the second multi-phase clock signals in response to the bit lock detection signal. Therefore, a jitter noise may be reduced and a size of a multi-phase clock generator included in the receiver may be reduced.

摘要翻译： 一种使用多相时钟信号的通信系统。 通信系统包括发射机和接收机。 发射机基于第一多相时钟信号输出第一数据和时钟信号，响应于指示第一数据是否被锁定的位锁定检测信号，对时钟信号执行粗略的锁定操作。 接收器从发送器接收第一数据和时钟信号，基于时钟信号产生第二多相时钟信号，通过基于第二多相时钟信号对第一数据进行采样产生第二数据，并执行精细锁定 响应于位锁定检测信号对第二多相时钟信号进行操作。 因此，可以减少抖动噪声，并且可以减少接收机中包括的多相时钟发生器的尺寸。

公开(公告)号：US07840831B2

公开(公告)日：2010-11-23

申请号：US11739389

申请日：2007-04-24

申请人： Young-Chan Jang

发明人： Young-Chan Jang

IPC分类号： G06F1/00 ,  H03K3/017

CPC分类号： H03K5/1565 ,  H03K5/135 ,  H03K5/15013

摘要： Phase correction circuits and methods for reducing phase skew between multiphase clock signals and a semiconductor device including the circuit are provided. The semiconductor device includes a phase correction circuit and an output buffer. The phase correction circuit corrects phase skew between multiphase clock signals and generates skew-corrected clock signals. The output buffer outputs data in synchronization with the skew-corrected clock signals. The phase correction circuit includes a phase corrector, a replication output buffer, a phase detector, and a controller. The phase corrector corrects a duty cycle of a first clock signal, a duty cycle of a second clock signal, and phase skew between the first and second clock signals and generates skew-corrected first and second clock signals. The replication output buffer has the same structure as a data output buffer and outputs replication data in synchronization with the skew-corrected first and second clock signals. The phase detector detects a phase error in data output from the replication output buffer and generates a detection signal. The controller controls the phase corrector in response to the detection signal. Accordingly, phase skew between multiphase clock signals can be reduced or eliminated.

摘要翻译： 提供了用于减少多相时钟信号与包括电路的半导体器件之间的相位偏移的相位校正电路和方法。 半导体器件包括相位校正电路和输出缓冲器。 相位校正电路校正多相时钟信号之间的相位偏移，并产生偏斜校正的时钟信号。 输出缓冲器与偏斜校正的时钟信号同步输出数据。 相位校正电路包括相位校正器，复制输出缓冲器，相位检测器和控制器。 相位校正器校正第一时钟信号的占空比，第二时钟信号的占空比，以及第一和第二时钟信号之间的相位偏移，并产生经偏差校正的第一和第二时钟信号。 复制输出缓冲器具有与数据输出缓冲器相同的结构，并且与经偏斜校正的第一和第二时钟信号同步地输出复制数据。 相位检测器检测从复制输出缓冲器输出的数据中的相位误差，并产生检测信号。 响应于检测信号，控制器控制相位校正器。 因此，可以减少或消除多相时钟信号之间的相位偏移。

公开(公告)号：US20100153792A1

公开(公告)日：2010-06-17

申请号：US12592271

申请日：2009-11-20

申请人： Young-Chan Jang

发明人： Young-Chan Jang

IPC分类号： G11B20/20 ,  G06F11/00

CPC分类号： G11C29/02 ,  G11C29/022 ,  G11C29/023 ,  G11C29/028

摘要： In a circuit and method for correcting skew among a plurality of communication channels used in communicating with a memory circuit, and in a memory controller and memory controlling method, and in a memory system and method, the circuit for correcting skew includes a transmitting circuit for transmitting a reference signal to input ends of the plurality of channels and through the plurality of channels, and a plurality of receiving circuits for receiving at the input ends of the plurality of channels a respective plurality of reflected signals, the reflected signals being reflected from respective output ends of the plurality of channels. A detection circuit receives the reflected signals and detects relative signal propagation time differences between the plurality of channels. A delay circuit coupled to at least one of the channels sets a signal propagation delay in the at least one of the channels based on the detected relative signal propagation time differences.

摘要翻译： 在用于与存储器电路通信使用的多个通信信道中的偏差校正的电路和方法中，以及在存储器控制器和存储器控制方法中，并且在存储器系统和方法中，用于校正偏斜的电路包括用于 将参考信号发送到多个信道的输入端并通过多个信道，以及多个接收电路，用于在多个信道的输入端接收相应的多个反射信号，反射信号从相应的多个信道反射 输出多个通道的端部。 检测电路接收反射信号并检测多个通道之间的相对信号传播时间差。 耦合到至少一个通道的延迟电路基于检测到的相对信号传播时间差设置至少一个信道中的信号传播延迟。

公开(公告)号：US07535293B2

公开(公告)日：2009-05-19

申请号：US11679802

申请日：2007-02-27

申请人： Young-Chan Jang

发明人： Young-Chan Jang

IPC分类号： H03F1/02

CPC分类号： H03F3/45475 ,  H03F3/45179 ,  H03F2203/45048 ,  H03F2203/45138 ,  H03F2203/45586 ,  H03F2203/45588 ,  H03F2203/45681

摘要： A preamplifier circuit includes a differential amplifying unit, an offset detection unit and a reference signal generation unit. The differential amplifying unit compares an input signal pair with a reference signal pair to generate an output signal pair. The offset detection unit detects an offset of the output signal pair received from the differential amplifying unit to generate a calibration signal in an offset calibration mode. The reference signal generation unit adjusts the reference signal pair based on the calibration signal, and the reference signal pair is fed-back to the differential amplifying unit.

摘要翻译： 前置放大器电路包括差分放大单元，偏移检测单元和参考信号产生单元。 差分放大单元将输入信号对与参考信号对进行比较以产生输出信号对。 偏移检测单元检测从差分放大单元接收的输出信号对的偏移量，以产生偏移校准模式中的校准信号。 参考信号生成单元基于校准信号来调整参考信号对，将参考信号对反馈到差分放大单元。

公开(公告)号：US20080036509A1

公开(公告)日：2008-02-14

申请号：US11739389

申请日：2007-04-24

申请人： Young-Chan Jang

发明人： Young-Chan Jang

IPC分类号： H03L7/00

CPC分类号： H03K5/1565 ,  H03K5/135 ,  H03K5/15013

摘要： Phase correction circuits and methods for reducing phase skew between multiphase clock signals and a semiconductor device including the circuit are provided. The semiconductor device includes a phase correction circuit and an output buffer. The phase correction circuit corrects phase skew between multiphase clock signals and generates skew-corrected clock signals. The output buffer outputs data in synchronization with the skew-corrected clock signals. The phase correction circuit includes a phase corrector, a replication output buffer, a phase detector, and a controller. The phase corrector corrects a duty cycle of a first clock signal, a duty cycle of a second clock signal, and phase skew between the first and second clock signals and generates skew-corrected first and second clock signals. The replication output buffer has the same structure as a data output buffer and outputs replication data in synchronization with the skew-corrected first and second clock signals. The phase detector detects a phase error in data output from the replication output buffer and generates a detection signal. The controller controls the phase corrector in response to the detection signal. Accordingly, phase skew between multiphase clock signals can be reduced or eliminated.

摘要翻译： 提供了用于减少多相时钟信号与包括电路的半导体器件之间的相位偏移的相位校正电路和方法。 半导体器件包括相位校正电路和输出缓冲器。 相位校正电路校正多相时钟信号之间的相位偏移，并产生偏斜校正的时钟信号。 输出缓冲器与偏斜校正的时钟信号同步输出数据。 相位校正电路包括相位校正器，复制输出缓冲器，相位检测器和控制器。 相位校正器校正第一时钟信号的占空比，第二时钟信号的占空比，以及第一和第二时钟信号之间的相位偏移，并产生经偏差校正的第一和第二时钟信号。 复制输出缓冲器具有与数据输出缓冲器相同的结构，并且与经偏斜校正的第一和第二时钟信号同步地输出复制数据。 相位检测器检测从复制输出缓冲器输出的数据中的相位误差，并产生检测信号。 响应于检测信号，控制器控制相位校正器。 因此，可以减少或消除多相时钟信号之间的相位偏移。