公开(公告)号：US06274477B1

公开(公告)日：2001-08-14

申请号：US09336554

申请日：1999-06-19

申请人： Gary Hong

发明人： Gary Hong

IPC分类号： H01L2128

CPC分类号： H01L21/7682

摘要： A method of fabricating a conductive line structure. A first dielectric layer is formed on a substrate. A conductive layer is formed on the first dielectric layer. The conductive layer is patterned to form an opening in the conductive layer. The opening exposes a portion of the first dielectric layer. A conformal stop layer is formed over the substrate. The conformal stop layer is conformal to the conductive layer. An oxide layer is formed in the opening. The oxide layer does not completely fill the opening. A portion of a sidewall of the opening is exposed. A spacer is formed on the exposed sidewall of the opening. The oxide layer is removed. A second dielectric layer is formed over the substrate to fill the opening. A void is formed in the second dielectric layer in the opening.

摘要翻译： 一种制造导线结构的方法。 在基板上形成第一电介质层。 在第一电介质层上形成导电层。 将导电层图案化以在导电层中形成开口。 开口暴露第一电介质层的一部分。 在衬底上形成共形停止层。 保形停止层与导电层共形。 在开口中形成氧化物层。 氧化层不完全填满开口。 开口侧壁的一部分露出。 间隔件形成在开口的暴露的侧壁上。 去除氧化物层。 第二介质层形成在衬底上以填充开口。 在开口中的第二介电层中形成空隙。

公开(公告)号：US06180471B2

公开(公告)日：2001-01-30

申请号：US09183062

申请日：1998-10-30

申请人： Peter Chang ,  Gary Hong ,  Joe Ko

发明人： Peter Chang ,  Gary Hong ,  Joe Ko

IPC分类号： H01L21336

CPC分类号： H01L29/6659 ,  H01L21/26586 ,  H01L29/7836

摘要： A method of fabricating a high voltage semiconductor device. A semiconductor substrate doped with a first type dopant and comprising a gate is provided. A cap oxide layer is formed on the gate optionally. A first ion implantation with a light second type dopant at a wide angle is performed to form a lightly doped region. A spacer is formed on a side wall of the gate. A second ion implantation with a heavy second type dopant is performed, so that a heavily doped region is formed within the lightly doped region.

摘要翻译： 一种制造高电压半导体器件的方法。 提供掺杂有第一类型掺杂剂并且包括栅极的半导体衬底。 可选地，在栅极上形成帽氧化物层。 进行具有广角的第二种光掺杂剂的第一离子注入以形成轻掺杂区域。 隔板形成在门的侧壁上。 执行具有重的第二类型掺杂剂的第二离子注入，使得在轻掺杂区域内形成重掺杂区域。

公开(公告)号：US06171909B2

公开(公告)日：2001-01-09

申请号：US09293434

申请日：1999-04-16

申请人： Yen-Lin Ding ,  Gary Hong

发明人： Yen-Lin Ding ,  Gary Hong

IPC分类号： H01L21336

CPC分类号： H01L27/11521 ,  H01L27/115

摘要： A method for forming a stacked gate of a flash memory cell is described. A first dielectric layer, a conductive layer and a silicon nitride layer are sequentially formed over a substrate. A photoresist pattern is formed over the silicon nitride layer. The silicon nitride layer, conductive layer, first dielectric layer and substrate are etched by using the photoresist pattern as an etching mask until forming a plurality of trenches in the substrate. An insulating layer is formed over the substrate, wherein the insulating layer has a surface level between a top surface of the conductive layer and a bottom surface of the conductive layer. A conductive spacer is formed on the sidewalls of the conductive layer and silicon nitride layer, wherein the conductive spacer and conductive layer serve as a first gate conductive layer. The silicon nitride layer is removed. A second dielectric layer and a second gate conductive layer are formed over the substrate. The second gate conductive layer, second dielectric layer and first gate conductive layer are patterned to form a control gate, a patterned dielectric layer and a floating gate, respectively.

摘要翻译： 描述了一种用于形成闪存单元的堆叠栅极的方法。 第一电介质层，导电层和氮化硅层依次形成在衬底上。 在氮化硅层上形成光刻胶图形。 通过使用光致抗蚀剂图案作为蚀刻掩模来蚀刻氮化硅层，导电层，第一介电层和衬底，直到在衬底中形成多个沟槽。 在衬底上形成绝缘层，其中绝缘层在导电层的顶表面和导电层的底表面之间具有表面水平。 导电间隔物形成在导电层和氮化硅层的侧壁上，其中导电间隔物和导电层用作第一栅极导电层。 去除氮化硅层。 第二电介质层和第二栅极导电层形成在衬底上。 将第二栅极导电层，第二介电层和第一栅极导电层图案化以分别形成控制栅极，图案化电介质层和浮置栅极。

公开(公告)号：US6150276A

公开(公告)日：2000-11-21

申请号：US313166

申请日：1999-05-17

申请人： Claymens Lee ,  Gary Hong

发明人： Claymens Lee ,  Gary Hong

IPC分类号： H01L21/336 ,  H01L29/49 ,  H01L21/311 ,  H01L21/302

CPC分类号： H01L29/6659 ,  H01L29/4983 ,  H01L29/4991 ,  H01L29/6656

摘要： A method for fabricating a metal-oxide semiconductor (MOS) transistor on a semiconductor substrate is described. The invention introduces an air chamber with a low dielectric constant between the gate and the source/drain region so as to lower the fringing electric field between the gate and the source/drain region. Moreover, the dielectric constant of the dielectric layer between the gate and the source/drain region is reduced. Therefore, the gate-to-drain capacitance is decreased in the MOS transistor.

摘要翻译： 描述了在半导体衬底上制造金属氧化物半导体（MOS）晶体管的方法。 本发明在栅极和源极/漏极区域之间引入具有低介电常数的气室，以便降低栅极和源极/漏极区域之间的边缘电场。 此外，栅极和源极/漏极区域之间的介电层的介电常数降低。 因此，MOS晶体管中的栅 - 漏电容减小。

公开(公告)号：US6140180A

公开(公告)日：2000-10-31

申请号：US54837

申请日：1998-04-03

申请人： Gary Hong

发明人： Gary Hong

IPC分类号： H01L21/02 ,  H01L27/108 ,  H01L21/8242

CPC分类号： H01L28/92 ,  H01L27/10814 ,  H01L28/84

摘要： A method of fabricating the storage capacitor for the memory cell units of DRAM IC devices is disclosed. The method is not constrained by the resolution limitations commonly seen in traditional photolithography. Self-aligned anisotropic procedure can be employed to form contact opening having reduced dimension. The smaller via formed in the opening can effectively prevent the situation in which the via is short-circuited with other components of the cell unit. Device fabrication yield rate can thus be improved.

摘要翻译： 公开了制造用于DRAM IC器件的存储单元单元的存储电容器的方法。 该方法不受传统光刻中常见的分辨率限制的限制。 可以采用自对准的各向异性方法来形成尺寸减小的接触开口。 在开口中形成的较小的通孔可以有效地防止通孔与电池单元的其它部件短路的情况。 因此可以提高装置制造成品率。

公开(公告)号：US6087218A

公开(公告)日：2000-07-11

申请号：US54836

申请日：1998-04-03

申请人： Gary Hong

发明人： Gary Hong

IPC分类号： H01L21/8242 ,  H01L27/108

CPC分类号： H01L27/10852 ,  H01L27/10817

摘要： A method for manufacturing DRAM capacitor that utilizes a self-aligned etching process for fabricating the lower electrode of a capacitor instead of a conventional photolithographic process whose processing accuracy is dependent upon the resolution of light source used. Using a polysilicon layer as a mask and a silicon nitride layer as an etching stop layer, the self-aligned etching process is carried out to form a rather narrow contact window in the insulating layer. By forming this narrow contact window, proper isolation between a word line and its neighboring conductive layer is ensured. Hence, device reliability is increased.

摘要翻译： 一种用于制造DRAM电容器的方法，其利用自对准蚀刻工艺来制造电容器的下电极，而不是常规的光刻工艺，其处理精度取决于所使用的光源的分辨率。 使用多晶硅层作为掩模和氮化硅层作为蚀刻停止层，进行自对准蚀刻工艺，以在绝缘层中形成相当窄的接触窗口。 通过形成该窄接触窗口，确保了字线与其相邻导电层之间的适当隔离。 因此，设备可靠性提高。

公开(公告)号：US6035530A

公开(公告)日：2000-03-14

申请号：US306130

申请日：1999-05-06

申请人： Gary Hong

发明人： Gary Hong

IPC分类号： H01L21/768 ,  H01L23/522 ,  H01R43/00

CPC分类号： H01L23/5222 ,  H01L21/7682 ,  H01L2924/0002 ,  Y10T29/49117 ,  Y10T29/49155 ,  Y10T29/49162 ,  Y10T29/49204 ,  Y10T29/49224

摘要： A method for manufacturing an interconnect. A substrate having a first dielectric layer and a barrier layer formed thereon is provided. A plurality of conductive wires is formed on the barrier layer. A second dielectric layer is formed on the barrier layer exposed by the conductive wires, wherein the second dielectric layer has a surface level between the top surfaces and the bottom surfaces of the conductive wires. A spacer is formed on each portion of the sidewalls of the conductive wires exposed by the second dielectric layer, wherein there is a gap between two adjacent spacers. The second dielectric layer is removed. A third dielectric layer is formed on the conductive wires, the spacer, the sidewalls of the conductive wires and the portion of the barrier layer exposed by the conductive wires and fills the gap to form an air cavity between the conductive wires under the spacer.

摘要翻译： 一种用于制造互连的方法。 提供了具有形成在其上的第一介电层和阻挡层的基板。 在阻挡层上形成多条导线。 在由导电线露出的阻挡层上形成第二电介质层，其中第二电介质层在导电丝的顶表面和底表面之间具有表面水平。 在由第二介电层暴露的导线的侧壁的每个部分上形成间隔物，其中在两个相邻间隔物之间​​存在间隙。 去除第二介电层。 第三电介质层形成在导电线上，间隔物，导线的侧壁和阻挡层的部分通过导线露出并填充间隙，以在间隔物之下的导线之间形成空气腔。

公开(公告)号：US6030882A

公开(公告)日：2000-02-29

申请号：US223200

申请日：1998-12-30

申请人： Gary Hong

发明人： Gary Hong

IPC分类号： H01L21/762 ,  H01L21/76

CPC分类号： H01L21/76237

摘要： A method for manufacturing shallow trench isolation structure in a substrate, in which by forming a doped region at the upper corners of a trench, the degree of oxidation in that region increases when the liner layer is formed over the exposed surface of the trench. Therefore, thickness of the liner layer at the upper corner regions of the trench is almost the same as in other regions. Consequently, a kink effect is prevented when a gate is subsequently formed over the active region of the substrate.

摘要翻译： 一种用于在衬底中制造浅沟槽隔离结构的方法，其中通过在沟槽的上角形成掺杂区域，当衬底层形成在沟槽的暴露表面上时，该区域中的氧化度增加。 因此，沟槽的上角区域的衬垫层的厚度与其他区域几乎相同。 因此，当栅极随后形成在衬底的有源区上时，可以防止扭结效应。

公开(公告)号：US5972752A

公开(公告)日：1999-10-26

申请号：US998725

申请日：1997-12-29

申请人： Gary Hong

发明人： Gary Hong

IPC分类号： H01L21/8247 ,  H01L27/115

CPC分类号： H01L27/11517 ,  H01L27/115

摘要： A method for forming a flash memory cell structure comprising the steps of providing a semiconductor substrate, and then sequentially forming a bottom conductive layer and a cap oxide layer over the substrate. Next, a pattern is defined in the conductive layer and the cap oxide layer. Subsequently, a thermal oxidation method is used to form a silicon oxide layer on the sidewalls of the bottom conductive layer. Then, a gate oxide layer is formed between the bottom conductive layers above the substrate. Thereafter, source/drain regions are formed in the semiconductor substrate. Then, spacer structures are formed adjacent to the silicon oxide layers. Using the spacer structures as masks, a portion of the gate oxide layer is etched. Then, the spacer structures are removed to expose the gate oxide layer. Next, a thermal oxidation method is used to form a tunneling oxide layer in the narrow region between the gate oxide layer. The tunneling oxide layer has a long narrow top profile. Finally, a floating gate layer, a dielectric layer and a control gate are sequentially formed to complete the flash memory cell structure.

摘要翻译： 一种用于形成闪存单元结构的方法，包括以下步骤：提供半导体衬底，然后在衬底上顺序形成底部导电层和帽氧化物层。 接下来，在导电层和盖氧化物层中限定图案。 随后，使用热氧化方法在底部导电层的侧壁上形成氧化硅层。 然后，在衬底上方的底部导电层之间形成栅氧化层。 此后，在半导体衬底中形成源/漏区。 然后，在氧化硅层附近形成间隔结构。 使用间隔结构作为掩模，蚀刻栅极氧化物层的一部分。 然后，去除间隔结构以露出​​栅极氧化物层。 接下来，使用热氧化法在栅极氧化层之间的窄区域形成隧道氧化物层。 隧道氧化物层具有长的窄的顶部轮廓。 最后，依次形成浮栅层，电介质层和控制栅，以完成闪存单元结构。

公开(公告)号：US5966600A

公开(公告)日：1999-10-12

申请号：US975496

申请日：1997-11-21

申请人： Gary Hong

发明人： Gary Hong

IPC分类号： H01L21/8242 ,  H01L27/108

CPC分类号： H01L27/10852 ,  H01L27/10817 ,  Y10S438/97

摘要： A DRAM is formed using a process which uses few critical lithography steps and which provides capacitor electrodes and bit line contacts in a self-aligned manner in a common set of processing steps. A multilayer stack including a gate oxide layer, a gate electrode layer, an etch stop layer, and a thicker sacrificial layer are provided over the active device regions of a semiconductor substrate. Photolithography and etching define gate electrodes and wiring lines with patterned etch stop layers and patterned sacrificial layers over and self-aligned with the gate electrodes and wiring lines. Source/drain regions are formed self aligned to the patterned stacks and then an insulating spacer is provided alongside the edges of the gate electrodes. A relatively thin, conformal polysilicon layer is provided over the patterned stacks and in contact with the source/drain regions adjacent the gate electrodes. A planarizing layer is provided to fill in the gaps over the polysilicon layer between the stacks of gate electrodes, patterned etch stop layers and patterned sacrificial layers. A polishing process is performed to remove the conductive layer over the patterned sacrificial layers. The exposed sacrificial layer and the planarizing layers are removed to provide lower capacitor electrodes with vertically extending fins and bit line contacts with landing pads that facilitate making contacts to the bit line contacts. Processing continues to provide a capacitor dielectric layer, an upper capacitor electrode and a bit line contact to complete the DRAM.

摘要翻译： 使用几个关键光刻步骤的方法形成DRAM，并且在一组共同的处理步骤中以自对准的方式提供电容器电极和位线接触。 在半导体衬底的有源器件区域上设置包括栅极氧化物层，栅电极层，蚀刻停止层和较厚牺牲层的多层堆叠。 光刻和蚀刻定义了具有图案化蚀刻停止层的栅极电极和布线，并且在栅极电极和布线之间对其进行了自对准的图案化牺牲层。 源极/漏极区域与图案化的叠层形成自对准，然后在栅电极的边缘旁边提供绝缘间隔物。 在图案化的堆叠上提供相对薄的共形多晶硅层，并且与邻近栅电极的源极/漏极区域接触。 提供平坦化层以填充栅极电极，图案化蚀刻停止层和图案化牺牲层之间的多晶硅层上的间隙。 执行抛光工艺以去除图案化的牺牲层上的导电层。 去除暴露的牺牲层和平坦化层以提供具有垂直延伸的鳍片的较低电容器电极和具有着陆焊盘的位线触点，其有助于与位线触点的接触。 处理继续提供电容器介电层，上电容器电极和位线接触来完成DRAM。