公开(公告)号：US06303455B1

公开(公告)日：2001-10-16

申请号：US09541450

申请日：2000-03-31

申请人： Chia-Hsin Hou ,  Tz-Guei Jung ,  Joe Ko

发明人： Chia-Hsin Hou ,  Tz-Guei Jung ,  Joe Ko

IPC分类号： H01L2120

CPC分类号： H01L28/40 ,  H01L28/60

摘要： A method for manufacturing a capacitor is provided in the present invention. The bottom electrode of the capacitor is a polysilicon layer, and the top electrode of the capacitor is a silicide layer. Since depletion regions cannot be generated in the metal layer or the suicide layer, and the resistivity of the metal layer or the silicide layer is smaller than a conventional polysilicon layer, so that operating speed and frequency of the capacitor are both increased.

摘要翻译： 本发明提供一种电容器的制造方法。 电容器的底部电极是多晶硅层，电容器的顶部电极是硅化物层。 由于在金属层或硅化物层中不能产生耗尽区，并且金属层或硅化物层的电阻率比常规多晶硅层小，所以电容器的工作速度和频率都增加。

公开(公告)号：US5576557A

公开(公告)日：1996-11-19

申请号：US422225

申请日：1995-04-14

申请人： Ming-Dou Ker ,  Chung-Yu Wu ,  Hun-Hsien Chang ,  Chung-Yuan Lee ,  Joe Ko

发明人： Ming-Dou Ker ,  Chung-Yu Wu ,  Hun-Hsien Chang ,  Chung-Yuan Lee ,  Joe Ko

IPC分类号： H01L27/02 ,  H01L29/74

CPC分类号： H01L27/0259 ,  H01L27/0251

摘要： An electrostatic discharge (ESD) circuit for protecting a semiconductor integrated circuit (IC) device is disclosed. One ESD circuit is located between each I/O buffering pad that connects to one lead pin and the internal circuitry of IC. The ESD circuit is connected to both power terminals. The ESD circuit comprises first and second low-voltage-trigger SCRs (LVTSCRs), each having an anode, a cathode, an anode gate and a cathode gate. The anode and anode gate of the first SCR are connected to a first power terminal, the cathode of the first SCR is connected to its I/O buffering pad, and the cathode gate of the first SCR is connected to the second power terminal. The ESD circuit further comprises a PMOS transistor having drain, source, gate, and bulk terminals. The PMOS transistor's gate, source and bulk terminals are connected to the first power terminal, the PMOS transistor drain terminal is connected to the cathode gate of the first SCR. The cathode and cathode gate of the second SCR are connected to the second power terminals. The anode of the second SCR is connected to its associated I/O buffering pads. The anode gate of the second SCR is connected to the first power terminal. The ESD circuit also comprises an NMOS transistor having drain, source, gate, and bulk terminals. The NMOS transistor's gate, source and bulk terminals are connected to the second power terminals. The NMOS transistor's drain terminal is connected to the anode gate of the second SCR.

摘要翻译： 公开了一种用于保护半导体集成电路（IC）器件的静电放电（ESD）电路。 一个ESD电路位于连接到一个引脚和IC的内部电路的每个I / O缓冲焊盘之间。 ESD电路连接到两个电源端子。 ESD电路包括第一和第二低电压触发SCR（LVTSCR），每个具有阳极，阴极，阳极栅极和阴极栅极。 第一SCR的阳极和阳极栅极连接到第一电源端子，第一SCR的阴极连接到其I / O缓冲焊盘，第一SCR的阴极栅极连接到第二电源端子。 ESD电路还包括具有漏极，源极，栅极和体积端子的PMOS晶体管。 PMOS晶体管的栅极，源极和体积端子连接到第一电源端子，PMOS晶体管漏极端子连接到第一SCR的阴极栅极。 第二SCR的阴极和阴极栅极连接到第二电源端子。 第二SCR的阳极连接到其相关的I / O缓冲垫。 第二SCR的阳极栅极连接到第一电源端子。 ESD电路还包括具有漏极，源极，栅极和体积端子的NMOS晶体管。 NMOS晶体管的栅极，源极和体积端子连接到第二个电源端子。 NMOS晶体管的漏极端子连接到第二SCR的阳极栅极。

公开(公告)号：US5565700A

公开(公告)日：1996-10-15

申请号：US426491

申请日：1995-04-20

申请人： Jih W. Chou ,  Joe Ko ,  Chun Y. Chang

发明人： Jih W. Chou ,  Joe Ko ,  Chun Y. Chang

IPC分类号： H01L21/265 ,  H01L21/336 ,  H01L29/78 ,  H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113

CPC分类号： H01L29/6659 ,  H01L21/26586 ,  H01L29/7836

摘要： A new surface counter-doped lightly doped source and drain integrated circuit field effect transistor device is described. A gate silicon oxide layer is formed on the silicon substrate. A layer of polysilicon is deposited over the gate silicon oxide layer and etched to form a gate electrode structure. A first ion implantation is performed at a tilt angle to form lightly doped drain regions in the semiconductor substrate wherein the lightly doped drain regions are partially overlapped by the gate electrode structure. A second ion implantation is performed at a larger tilt angle and lower energy than the first ion implantation wherein the second ion implantation counter-dopes the surface of the lightly doped drain regions to form a very lightly doped drain layer thus making the lightly doped drain regions buried regions. A thin layer of silicon oxide is deposited over the surface of the polysilicon gate electrode structure and is anisotropically etched to form ultra thin spacers on the sidewalls of the polysilicon gate electrode structure. A third ion implantation is performed with no tilt angle to complete formation of the lightly doped drain regions. A glasseous layer is deposited over all surfaces of the substrate and flowed followed by metallization and passivation to complete manufacture of the integrated circuit.

摘要翻译： 描述了新的表面反掺杂轻掺杂源极和漏极集成电路场效应晶体管器件。 在硅衬底上形成栅氧化硅层。 一层多晶硅沉积在栅极氧化硅层上并被蚀刻以形成栅电极结构。 以倾斜角度执行第一离子注入，以在半导体衬底中形成轻掺杂漏极区域，其中轻掺杂漏极区域被栅电极结构部分地重叠。 以比第一离子注入更大的倾斜角度和更低的能量执行第二离子注入，其中第二离子注入反掺杂轻掺杂的漏极区的表面以形成非常轻掺杂的漏极层，从而使轻掺杂漏极区 埋葬地区。 氧化硅薄层沉积在多晶硅栅电极结构的表面上，并被各向异性蚀刻以在多晶硅栅电极结构的侧壁上形成超薄间隔物。 执行没有倾斜角的第三离子注入以完成轻掺杂漏极区的形成。 在基板的所有表面上沉积一层胶层，然后流动，随后进行金属化和钝化以完成集成电路的制造。

公开(公告)号：US5434108A

公开(公告)日：1995-07-18

申请号：US124647

申请日：1993-09-22

申请人： Joe Ko ,  Chen-Chiu Hsue

发明人： Joe Ko ,  Chen-Chiu Hsue

IPC分类号： H01L21/28 ,  H01L21/3213 ,  H01L21/465

CPC分类号： H01L21/28123 ,  H01L21/32136 ,  H01L21/32137

摘要： A method of subjecting an integrated circuit, having electrically grounded elements and large first metal regions on its surface which are connected to device structures, to a plasma process, is described. Large first metal regions are connected to the electrically grounded elements. The integrated circuit is placed in a chamber for accomplishing the plasma process. The integrated circuit is subjected to the plasma process such that the connecting of the large first metal regions to the electrically grounded elements prevents damage to the device structures. The integrated circuit is removed from the chamber. Finally, the large first metal regions are disconnected from the electrically grounded elements.

摘要翻译： 描述了将具有电接地元件的集成电路及其与器件结构连接的表面上的大的第一金属区域进行等离子体处理的方法。 大的第一金属区域连接到电接地元件。 将集成电路放置在用于完成等离子体处理的室中。 对集成电路进行等离子体处理，使得大的第一金属区域与电接地元件的连接防止对器件结构的损坏。 集成电路从腔室中取出。 最后，大的第一金属区域与电接地元件断开。

公开(公告)号：US06309925B1

公开(公告)日：2001-10-30

申请号：US09643211

申请日：2000-08-22

申请人： Tz-Guei Jung ,  Chia-Hsin Hou ,  Joe Ko

发明人： Tz-Guei Jung ,  Chia-Hsin Hou ,  Joe Ko

IPC分类号： H01L218242

CPC分类号： H01L27/0629 ,  H01L28/40

摘要： A method for manufacturing a capacitor. A semiconductor substrate is divided into a peripheral circuit region and a memory cell region. An isolation structure is formed in the memory cell region. A gate oxide layer is formed over the substrate outside the isolation structure. A polysilicon layer is formed over the gate oxide layer and the isolation structure. The polysilicon layer and the gate oxide layer are patterned to form a bottom electrode above the isolation structure. In the meantime a polysilicon gate electrode is also formed above the peripheral circuit region. Spacers are formed on the sidewalls of the polysilicon gate electrode and the bottom electrode. A metal silicide layer is formed over the bottom electrode and the polysilicon gate electrode. A dielectric layer is formed over the metal silicide layer above the bottom electrode. A metallic layer is formed over the dielectric layer to form a capacitor.

摘要翻译： 一种制造电容器的方法。 半导体衬底被分成外围电路区域和存储单元区域。 在存储单元区域中形成隔离结构。 在隔离结构外部的衬底上形成栅氧化层。 在栅极氧化物层和隔离结构上形成多晶硅层。 图案化多晶硅层和栅极氧化物层以在隔离结构上方形成底部电极。 同时，在外围电路区域上方也形成多晶硅栅电极。 隔板形成在多晶硅栅电极和底电极的侧壁上。 在底部电极和多晶硅栅电极上形成金属硅化物层。 在底部电极上方的金属硅化物层上形成介电层。 在电介质层上形成金属层以形成电容器。

公开(公告)号：US06271082B1

公开(公告)日：2001-08-07

申请号：US09557345

申请日：2000-04-25

申请人： Chia-Hsin Hou ,  Jyh-Kuang Lin ,  Tz-Guei Jung ,  Joe Ko

发明人： Chia-Hsin Hou ,  Jyh-Kuang Lin ,  Tz-Guei Jung ,  Joe Ko

IPC分类号： H01L218242

CPC分类号： H01L28/60 ,  H01L21/3212 ,  H01L21/76807 ,  H01L28/55

摘要： A method for fabricating a capacitor is applicable to a fabrication process for a mixed circuit. The method involves forming a first dielectric layer, a stop layer, and a second dielectric layer on a substrate having a conductive region. A first opening is then formed in the second dielectric layer, followed by forming a second opening in the stop layer and the first dielectric layer, so that the first opening and the second opening form a dual damascene opening for exposing the conductive region. The dual damascene opening is filled with a first conductive layer, so as to form a via plug and a lower electrode of the capacitor for connecting to the conductive region. A third dielectric layer, which is located between the lower electrode and a subsequent formed upper electrode, is then formed over the substrate, so that the lower electrode and a part of the second dielectric layer adjacent to the lower electrode are completely covered by the third dielectric layer. A patterned second conductive layer is formed on a part of the third dielectric layer, whereby an upper electrode for completely covering the lower electrode is formed.

摘要翻译： 制造电容器的方法适用于混合电路的制造工艺。 该方法包括在具有导电区域的基底上形成第一介电层，停止层和第二介质层。 然后在第二电介质层中形成第一开口，随后在停止层和第一电介质层中形成第二开口，使得第一开口和第二开口形成用于暴露导电区域的双镶嵌开口。 双镶嵌开口填充有第一导电层，以便形成用于连接到导电区域的电容器的通孔塞和下电极。 然后在衬底上形成位于下电极和随后形成的上电极之间的第三电介质层，使得下电极和与下电极相邻的第二电介质层的一部分被第三电介质层完全覆盖 电介质层。 图案化的第二导电层形成在第三介电层的一部分上，由此形成用于完全覆盖下电极的上电极。

公开(公告)号：US6046079A

公开(公告)日：2000-04-04

申请号：US790273

申请日：1997-01-28

申请人： Joe Ko ,  Chung-Yuan Lee

发明人： Joe Ko ,  Chung-Yuan Lee

IPC分类号： H01L21/763 ,  H01L27/092 ,  H01L21/30 ,  H01L21/335

CPC分类号： H01L27/0921 ,  H01L21/763

摘要： A MOSFET integrated circuit device comprises a lightly doping a semiconductor substrate, with wells formed within the substrate doped with an opposite value dopant, forming a plurality of doped regions within the surface of the substrate and within the surface of the wells, the improvement comprising opening a trench about the periphery of the wells, and filling the trench with a relatively highly conductive material as a guard structure.

摘要翻译： MOSFET集成电路器件包括轻掺杂半导体衬底，其中形成在衬底内的阱掺杂有相反值的掺杂剂，在衬底的表面内和阱的表面内形成多个掺杂区域，其改进包括打开 围绕孔的周边的沟槽，以及用相对较高导电性的材料填充沟槽作为防护结构。

公开(公告)号：US5602049A

公开(公告)日：1997-02-11

申请号：US322939

申请日：1994-10-04

申请人： Jemmy Wen ,  Joe Ko

发明人： Jemmy Wen ,  Joe Ko

IPC分类号： H01L21/76 ,  H01L21/762 ,  H01L21/8244 ,  H01L27/11 ,  H01L21/70 ,  H01L27/00

CPC分类号： H01L27/1112 ,  H01L21/76 ,  H01L21/76202 ,  H01L27/11 ,  Y10S257/904

摘要： An improved SRAM cell having ultra-high density and methods for fabrication are described. Each SRAM cell, according to the present invention, has its own buried structure, including word lines (i.e., gate regions) and bit lines (i.e., source/drain regions), thus increasing the cell ratio of channel width of cell transistor to that of pass transistor to keep the data stored in the cell transistor more stable without increasing the area per cell. In addition, according to the present invention, the field isolation between active regions is not field oxide but blankly ion-implanted silicon substrate. Therefore, SRAM cells can be densely integrated due to the absence of bird's beak encroachment. Since the present invention has more planar topography, it is easily adapted to the VLSI process, which is always restricted by the limit of resolution of photolithography, thus increasing the degree of integration.

摘要翻译： 描述了具有超高密度的改进的SRAM单元和制造方法。 根据本发明的每个SRAM单元具有其自己的掩埋结构，包括字线（即栅极区）和位线（即，源极/漏极区），从而将单元晶体管的沟道宽度的单元比增加到 的传输晶体管，以保持存储在单元晶体管中的数据更稳定，而不增加每个单元的面积。 此外，根据本发明，有源区之间的场隔离不是场氧化物而是空心离子注入的硅衬底。 因此，由于没有鸟喙侵入，SRAM单元可以密集地集成。 由于本发明具有更平坦的形貌，所以易于适应于VLSI工艺，VLSI工艺总是受到光刻分辨率的限制，从而增加了集成度。

公开(公告)号：US5574302A

公开(公告)日：1996-11-12

申请号：US518708

申请日：1995-08-24

申请人： Jemmy Wen ,  Water Lur ,  Joe Ko

发明人： Jemmy Wen ,  Water Lur ,  Joe Ko

IPC分类号： H01L21/336 ,  H01L21/8234 ,  H01L27/112 ,  H01L29/08 ,  H01L29/417 ,  H01L29/423 ,  H01L29/76 ,  H01L29/94 ,  H01L31/062

CPC分类号： H01L29/41766 ,  H01L21/823418 ,  H01L27/112 ,  H01L29/0847 ,  H01L29/66575 ,  H01L29/66787 ,  H01L29/78

摘要： This invention describes a diving channel device structure and a method of forming the diving channel device structure using deep vertical trenches formed in a silicon substrate crossing shallow vertical trenches formed in the same silicon substrate. The deep vertical trenches are filled with a first heavily doped polysilicon to form the sources and drains of field effect transistors. The shallow vertical trenches are filled with a second highly doped polysilicon to form the gates of the transistors. The device structure provides reduced drain and source resistance which remains nearly constant when the device is scaled to smaller dimensions. The device structure also provides reduced leakage currents and a plane topography. The device structure forms a large effective channel width when the device is scaled to smaller dimensions.

摘要翻译： 本发明描述了一种潜水通道装置结构，以及使用形成在与在同一硅衬底中形成的浅垂直沟槽的硅衬底中形成的深垂直沟槽形成潜水通道器件结构的方法。 深垂直沟槽填充有第一重掺杂多晶硅以形成场效应晶体管的源极和漏极。 浅的垂直沟槽用第二高掺杂多晶硅填充以形成晶体管的栅极。 器件结构提供了降低的漏极和源极电阻，当器件被缩放到更小的尺寸时，其保持几乎恒定。 器件结构还提供减少的漏电流和平面形貌。 当设备缩放到更小的尺寸时，器件结构形成大的有效通道宽度。

公开(公告)号：US5559352A

公开(公告)日：1996-09-24

申请号：US354373

申请日：1994-12-12

申请人： Chen-Chiu Hsue ,  Joe Ko

发明人： Chen-Chiu Hsue ,  Joe Ko

IPC分类号： H01L27/02 ,  H01L29/76

CPC分类号： H01L27/0266

摘要： A method of forming an ESD protection device with reduced breakdown voltage, simultaneously with an integrated circuit which includes FET devices, and the resultant device structure, are described. A silicon substrate is provided on which there are field oxide regions, gates, and active regions. A first ion implant of a conductivity-imparting dopant is performed in a vertical direction into the active regions of the ESD protection device and the FET devices. A first insulating layer is formed over the ESD protection device and the FET devices, and over the field oxide regions. The first insulating layer is patterned to create spacers adjacent to the gates of both the ESD protection device and the FET devices. A second ion implant of a conductivity-imparting dopant with higher concentration than dopant from the first ion implant is performed into active regions of both the ESD protection device and the FET devices. A second insulating layer is formed over the ESD protection device and the FET devices, and over the field oxide regions. The second insulating layer is patterned to form contact openings to the active regions. Finally, a third ion implant of a conductivity-imparting dopant, with opposite conductivity from the first and second ion implants, having equal concentration to dopant from the first ion implant, is performed through the contact openings into active regions of the ESD protection device.

摘要翻译： 描述了与包括FET器件的集成电路同时形成具有降低的击穿电压的ESD保护器件的方法以及所得到的器件结构。 提供硅基板，其上有场氧化物区域，栅极和有源区域。 导电性赋予掺杂剂的第一离子注入在垂直方向上进入ESD保护器件和FET器件的有源区。 在ESD保护器件和FET器件上以及场氧化物区域上形成第一绝缘层。 图案化第一绝缘层以产生与ESD保护器件和FET器件的栅极相邻的间隔物。 与来自第一离子注入的掺杂剂相比，具有更高浓度的导电性赋予掺杂剂的第二离子注入被执行到ESD保护器件和FET器件的有源区。 在ESD保护器件和FET器件上以及场氧化物区域上形成第二绝缘层。 图案化第二绝缘层以形成到活性区的接触开口。 最后，通过所述接触开口将与所述第一和第二离子注入相反的具有与所述第一和第二离子注入物相反的导电性的第三离子注入与所述第一离子注入物的掺杂剂相同地进入到所述ESD保护器件的有源区。