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    SHARED CLOCK DUAL EDGE-TRIGGERED FLIP-FLOP CIRCUIT
    25.
    发明公开
    SHARED CLOCK DUAL EDGE-TRIGGERED FLIP-FLOP CIRCUIT 审中-公开

    公开(公告)号：US20240204782A1

    公开(公告)日：2024-06-20

    申请号：US18081907

    申请日：2022-12-15

    Applicant: Intel Corporation

    Inventor： Amit Agarwal ,  Steven K. Hsu ,  Ram Kumar Krishnamurthy

    IPC: H03K19/094 ,  H03K19/017 ,  H03K19/1776

    CPC classification number: H03K19/09425 ,  H03K19/01728 ,  H03K19/1776

    Abstract: Some embodiments include an apparatus having a flip-flop circuit, which can include a first tristate inverter, a second tristate inverter including an input node coupled to an input node of the first tristate inverter; a first additional inverter including, and a second additional inverter including an output node coupled to an output node of the first additional inverter; a first memory including a first memory node coupled to an output node of the second tristate inverter, and a first additional memory node coupled to an input node of the first additional inverter; and a second memory including a second memory node coupled to an output node of the first tristate inverter, and a second additional memory node coupled to an input node of the second additional inverter.

    APPARATUS AND METHOD FOR APPROXIMATE TRILINEAR INTERPOLATION FOR SCENE RECONSTRUCTION
    27.
    发明申请
    APPARATUS AND METHOD FOR APPROXIMATE TRILINEAR INTERPOLATION FOR SCENE RECONSTRUCTION 有权

    公开(公告)号：US20210407168A1

    公开(公告)日：2021-12-30

    申请号：US17070095

    申请日：2020-10-14

    Applicant: Intel Corporation

    Inventor： Vivek De ,  Ram Krishnamurthy ,  Amit Agarwal ,  Steven Hsu ,  Monodeep Kar

    IPC: G06T15/00 ,  G06T15/06

    Abstract: A method comprising: dividing a 3D space into a voxel grid comprising a plurality of voxels; associating a plurality of distance values with the plurality of voxels, each distance value based on a distance to a boundary of an object; selecting an approximate interpolation mode for stepping a ray through a first one or more voxels of the 3D space responsive to the first one or more voxels having distance values greater than a threshold; and detecting the ray reaching a second one or more voxels having distance values less than the first threshold; and responsively selecting a precise interpolation mode for stepping the ray through the second one or more voxels.

    LOW-POWER SINGLE-EDGE TRIGGERED FLIP-FLOP, AND TIME BORROWING INTERNALLY STITCHED FLIP-FLOP
    29.
    发明申请
    LOW-POWER SINGLE-EDGE TRIGGERED FLIP-FLOP, AND TIME BORROWING INTERNALLY STITCHED FLIP-FLOP 有权

    公开(公告)号：US20210281250A1

    公开(公告)日：2021-09-09

    申请号：US16813558

    申请日：2020-03-09

    Applicant: Intel Corporation

    Inventor： Steven Hsu ,  Amit Agarwal ,  Simeon Realov ,  Satish Damaraju ,  Ram Krishnamurthy

    IPC: H03K3/037 ,  G06F3/06 ,  G01R31/3177 ,  G06F1/06

    Abstract: A new family of shared clock single-edge triggered flip-flops that reduces a number of internal clock devices from 8 to 6 devices to reduce clock power. The static pass-gate master-slave flip-flop has no performance penalty compared to the flip-flops with 8 clock devices thus enabling significant power reduction. The flip-flop intelligently maintains the same polarity between the master and slave stages which enables the sharing of the master tristate and slave state feedback clock devices without risk of charge sharing across all combinations of clock and data toggling. Because of this, the state of the flip-flop remains undisturbed, and is robust across charge sharing noise. A multi-bit time borrowing internal stitched flip-flop is also described, which enables internal stitching of scan in a high performance time-borrowing flip-flop without incurring increase in layout area.

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