公开(公告)号：US20210391478A1

公开(公告)日：2021-12-16

申请号：US16902069

申请日：2020-06-15

Applicant: Intel Corporation

Inventor： Kirby MAXEY ,  Chelsey DOROW ,  Kevin P. O'BRIEN ,  Carl NAYLOR ,  Ashish Verma PENUMATCHA ,  Tanay GOSAVI ,  Uygar E. AVCI ,  Shriram SHIVARAMAN

IPC: H01L29/786 ,  H01L29/423 ,  H01L29/66 ,  H01L29/24

Abstract: Embodiments include two-dimensional (2D) semiconductor sheet transistors and methods of forming such devices. In an embodiment, a semiconductor device comprises a stack of 2D semiconductor sheets, where individual ones of the 2D semiconductor sheets have a first end and a second end opposite from the first end. In an embodiment, a first spacer is over the first end of the 2D semiconductor sheets, and a second spacer is over the second end of the 2D semiconductor sheets. Embodiments further comprise a gate electrode between the first spacer and the second spacer, a source contact adjacent to the first end of the 2D semiconductor sheets, and a drain contact adjacent to the second end of the 2D semiconductor sheets.

公开(公告)号：US20210167182A1

公开(公告)日：2021-06-03

申请号：US16700757

申请日：2019-12-02

Applicant: Intel Corporation

Inventor： Seung Hoon SUNG ,  Ashish Verma PENUMATCHA ,  Sou-Chi CHANG ,  Devin MERRILL ,  I-Cheng TUNG ,  Nazila HARATIPOUR ,  Jack T. KAVALIEROS ,  Ian A. YOUNG ,  Matthew V. METZ ,  Uygar E. AVCI ,  Chia-Ching LIN ,  Owen LOH ,  Shriram SHIVARAMAN ,  Eric Charles MATTSON

IPC: H01L29/51 ,  H01L29/78 ,  H01L29/66 ,  H01L27/088 ,  H01L29/423 ,  H01L21/8234

Abstract: A integrated circuit structure comprises a fin extending from a substrate. The fin comprises source and drain regions and a channel region between the source and drain regions. A multilayer high-k gate dielectric stack comprises at least a first high-k material and a second high-k material, the first high-k material extending conformally over the fin over the channel region, and the second high-k material conformal to the first high-k material, wherein either the first high-k material or the second high-k material has a modified material property different from the other high-k material, wherein the modified material property comprises at least one of ferroelectricity, crystalline phase, texturing, ordering orientation of the crystalline phase or texturing to a specific crystalline direction or plane, strain, surface roughness, and lattice constant and combinations thereof. A gate electrode ix over and on a topmost high-k material in the multilayer high-k gate dielectric stack. A selector element is above the metal layer.

公开(公告)号：US20210111179A1

公开(公告)日：2021-04-15

申请号：US16599422

申请日：2019-10-11

Applicant: Intel Corporation

Inventor： Shriram SHIVARAMAN ,  Sou-Chi CHANG ,  Ashish Verma PENUMATCHA ,  Nazila HARATIPOUR ,  Uygar E. AVCI

IPC: H01L27/11514 ,  H01L49/02 ,  H01L27/11507 ,  G11C11/22 ,  H01L27/11504

Abstract: A memory device comprises a bitline along a first direction. A wordline is along a second direction orthogonal to the first direction. An access transistor is coupled to the bitline and the wordline. A first ferroelectric capacitor is vertically aligned with and coupled to the access transistor. A second ferroelectric capacitor is vertically aligned with the first ferroelectric capacitor and coupled to the access transistor, wherein both the first ferroelectric capacitor and the second ferroelectric capacitor are controlled by the access transistor.

公开(公告)号：US20200312950A1

公开(公告)日：2020-10-01

申请号：US16369737

申请日：2019-03-29

Applicant: Intel Corporation

Inventor： Nazila HARATIPOUR ,  Chia-Ching LIN ,  Sou-Chi CHANG ,  Ashish Verma PENUMATCHA ,  Owen LOH ,  Mengcheng LU ,  Seung Hoon SUNG ,  Ian A. YOUNG ,  Uygar AVCI ,  Jack T. KAVALIEROS

IPC: H01L49/02 ,  H01L27/11585 ,  H01L23/522 ,  H01G4/30 ,  H01G4/012

Abstract: A capacitor is disclosed that includes a first metal layer and a seed layer on the first metal layer. The seed layer includes a polar phase crystalline structure. The capacitor also includes a ferroelectric layer on the seed layer and a second metal layer on the ferroelectric layer.

公开(公告)号：US20240186416A1

公开(公告)日：2024-06-06

申请号：US18414290

申请日：2024-01-16

Applicant: Intel Corporation

Inventor： Kevin P. O'Brien ,  Carl NAYLOR ,  Chelsey DOROW ,  Kirby MAXEY ,  Tanay GOSAVI ,  Ashish Verma PENUMATCHA ,  Shriram SHIVARAMAN ,  Chia-Ching LIN ,  Sudarat LEE ,  Uygar E. AVCI

IPC: H01L29/78 ,  H01L21/02 ,  H01L29/06 ,  H01L29/24 ,  H01L29/423 ,  H01L29/66

CPC classification number: H01L29/7853 ,  H01L29/0673 ,  H01L29/24 ,  H01L29/42392 ,  H01L29/6653 ,  H01L29/6681 ,  H01L21/02568 ,  H01L21/0262

Abstract: Embodiments disclosed herein comprise semiconductor devices with two dimensional (2D) semiconductor channels and methods of forming such devices. In an embodiment, the semiconductor device comprises a source contact and a drain contact. In an embodiment, a 2D semiconductor channel is between the source contact and the drain contact. In an embodiment, the 2D semiconductor channel is a shell.

公开(公告)号：US20240006481A1

公开(公告)日：2024-01-04

申请号：US17853547

申请日：2022-06-29

Applicant: Intel Corporation

Inventor： Chelsey DOROW ,  Kevin P. O'BRIEN ,  Sudarat LEE ,  Ande KITAMURA ,  Ashish Verma PENUMATCHA ,  Carl H. NAYLOR ,  Kirby MAXEY ,  Chia-Ching LIN ,  Scott B. CLENDENNING ,  Uygar E. AVCI

IPC: H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/786

CPC classification number: H01L29/0673 ,  H01L29/42392 ,  H01L29/6681 ,  H01L29/66545 ,  H01L29/78696

Abstract: Embodiments disclosed herein include transistors and methods of forming transistors. In an embodiment, the transistor comprises a source region, a drain region, a first semiconductor channel between the source region and the drain region, and a second semiconductor channel between the source region and the drain region over the first semiconductor channel. In an embodiment, an insulator is around the source region, the drain region, the first semiconductor channel, and the second semiconductor channel. In an embodiment, a first access hole is in the insulator adjacent to a first edge of the first semiconductor channel, and a second access hole is in the insulator adjacent to a second edge of the first semiconductor channel.

公开(公告)号：US20230317783A1

公开(公告)日：2023-10-05

申请号：US17709365

申请日：2022-03-30

Applicant: Intel Corporation

Inventor： Kirby MAXEY ,  Carl H. NAYLOR ,  Uygar E. AVCI ,  Chelsey DOROW ,  Kevin P. O'BRIEN ,  Scott B. CLENDENNING ,  Matthew V. METZ ,  Chia-Ching LIN ,  Sudarat LEE ,  Ashish Verma PENUMATCHA

IPC: H01L29/06 ,  H01L29/786 ,  H01L21/8234 ,  H01L29/66

CPC classification number: H01L29/0665 ,  H01L29/78696 ,  H01L29/66742 ,  H01L21/823412 ,  H01L29/78651

Abstract: Embodiments described herein may be related to forming nano ribbon transistors using layered 2D semiconductor channels. The layered 2D semiconductor channels may be created by forming a scaffold structure that has a first edge that extends from a silicon-based substrate, and a second edge opposite the first edge that is distal to the silicon based substrate. Alternating layers of 2D semiconductor material and a 3D semiconductor material may then be built on the second edge of the scaffold structure. In embodiments, the 3D semiconductor material may then be removed and a gate material deposited around at least a portion of the layers of 2D semiconductor material.

公开(公告)号：US20230111323A1

公开(公告)日：2023-04-13

申请号：US17485325

申请日：2021-09-25

Applicant: Intel Corporation

Inventor： Rahul RAMAMURTHY ,  Ashish Verma PENUMATCHA ,  Sarah ATANASOV ,  Seung Hoon SUNG ,  Inanc MERIC ,  Uygar E. AVCI

IPC: H01L29/423 ,  H01L29/786 ,  H01L29/06 ,  H01L21/225

Abstract: Embodiments described herein may be related to apparatuses, processes, and techniques related to minimizing sub channel leakage within stacked GAA nanosheet transistors by doping an oxide layer on top of the sub channel. In embodiments, this doping may include selective introduction of charge species, for example carbon, within the gate oxide layer. Other embodiments may be described and/or claimed.

公开(公告)号：US20230101604A1

公开(公告)日：2023-03-30

申请号：US17485314

申请日：2021-09-24

Applicant: Intel Corporation

Inventor： Ashish Verma PENUMATCHA ,  Uygar E. AVCI ,  Tanay GOSAVI ,  Shriram SHIVARAMAN ,  Carl H. NAYLOR ,  Chelsey DOROW ,  Ian A. YOUNG ,  Nazila HARATIPOUR ,  Kevin P. O'BRIEN

IPC: H01L29/76 ,  H01L27/11556 ,  H01L27/11582 ,  H01L27/11597 ,  H01L29/24

Abstract: Embodiments of the disclosure are directed to advanced integrated circuit structure fabrication and, in particular, to three-dimensional (3D) memory devices with transition metal dichalcogenide (TMD) channels. Other embodiments may be disclosed or claimed.

公开(公告)号：US20230100952A1

公开(公告)日：2023-03-30

申请号：US17485291

申请日：2021-09-24

Applicant: Intel Corporation

Inventor： I-Cheng TUNG ,  Ashish Verma PENUMATCHA ,  Seung Hoon SUNG ,  Sarah ATANASOV ,  Jack T. KAVALIEROS ,  Matther V. METZ ,  Uygar E. AVCI ,  Rahul RAMAMURTHY ,  Chia-Ching LIN ,  Kaan OGUZ

IPC: H01L29/49 ,  H01L29/06 ,  H01L29/423 ,  H01L29/78 ,  H01L29/786 ,  H01L21/02 ,  H01L21/28 ,  H01L29/66

Abstract: Embodiments disclosed herein include transistors and transistor gate stacks. In an embodiment, a transistor gate stack comprises a semiconductor channel. In an embodiment, an interlayer (IL) is over the semiconductor channel. In an embodiment, the IL has a thickness of 1 nm or less and comprises zirconium. In an embodiment, a gate dielectric is over the IL, and a gate metal over the gate dielectric.