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21.发明授权公开(公告)号：US10403602B2
公开(公告)日：2019-09-03
申请号：US15637935
申请日：2017-06-29
Applicant: Intel Corporation
Inventor： Bernd Waidhas , Georg Seidemann , Andreas Augustin , Laurent Millou , Andreas Wolter , Reinhard Mahnkopf , Stephan Stoeckl , Thomas Wagner
IPC: H01L21/48 , H01L25/065 , H01L23/48 , G06F15/76 , H01L25/00
Abstract: A semiconductive device stack, includes a baseband processor die with an active surface and a backside surface, and a recess in the backside surface. A recess-seated device is disposed in the recess, and a through-silicon via in the baseband processor die couples the baseband processor die at the active surface to the recess-seated die at the recess. A processor die is disposed on the baseband processor die backside surface, and a memory die is disposed on the processor die. The several dice are coupled by through-silicon via groups.
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公开(公告)号：US10394280B2
公开(公告)日：2019-08-27
申请号：US15870819
申请日：2018-01-12
Applicant: INTEL CORPORATION
Inventor： Thorsten Meyer , Dirk Plenkers , Hans-Joachim Barth , Bernd Waidhas , Yen Hsiang Chew , Kooi Chi Ooi , Howe Yin Loo
Abstract: Embodiments of wearable electronic devices, components thereof, and related systems and techniques are disclosed herein. For example, a wearable electronic device may include a wearable support structure having a first surface and a second surface; a first electrode located at the first surface, wherein, when the wearable electronic device is worn by a user on a portion of the user's body, the first electrode is arranged to contact the user's skin in the portion of the user's body; a second electrode located at the second surface, wherein, when the wearable electronic device is worn by a user on the portion of the user's body, the second electrode is arranged to not contact the user's skin in the portion of the user's body; and a resistance switch having first and second input terminals coupled to the first and second electrodes, respectively. Other embodiments may be disclosed and/or claimed.
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公开(公告)号：US20160274621A1
公开(公告)日：2016-09-22
申请号：US14778070
申请日：2014-11-12
Applicant: INTEL CORPORATION
Inventor： Thorsten Meyer , Dirk Plenkers , Hans-Joachim Barth , Bernd Waidhas , Yen Hsiang Chew , Kooi Chi Ooi , Howe Yin Loo
CPC classification number: G06F1/163 , B29C39/021 , B29C39/10 , B29C65/4825 , B29L2031/3481 , G02C5/143 , G02C11/10
Abstract: Embodiments of wearable electronic devices, components thereof, and related systems and techniques are disclosed herein. For example, a wearable electronic device may include a wearable support structure having a first surface and a second surface; a first electrode located at the first surface, wherein, when the wearable electronic device is worn by a user on a portion of the user's body, the first electrode is arranged to contact the user's skin in the portion of the user's body; a second electrode located at the second surface, wherein, when the wearable electronic device is worn by a user on the portion of the user's body, the second electrode is arranged to not contact the user's skin in the portion of the user's body; and a resistance switch having first and second input terminals coupled to the first and second electrodes, respectively. Other embodiments may be disclosed and/or claimed.
Abstract translation: 可穿戴式电子设备，其组件以及相关系统和技术的实施例在此公开。 例如，可穿戴电子设备可以包括具有第一表面和第二表面的可穿戴支撑结构; 位于所述第一表面的第一电极，其中当所述可穿戴电子设备被所述用户佩戴在所述用户身体的一部分上时，所述第一电极布置成在所述用户身体的所述部分中接触所述用户的皮肤; 位于所述第二表面的第二电极，其中，当所述可佩戴的电子装置被使用者佩戴在所述使用者身体的所述部分上时，所述第二电极被布置成在所述使用者身体的所述部分中不接触所述使用者的皮肤; 以及电阻开关，其具有分别耦合到第一和第二电极的第一和第二输入端子。 可以公开和/或要求保护其他实施例。
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公开(公告)号：US20250132259A1
公开(公告)日：2025-04-24
申请号：US18989232
申请日：2024-12-20
Applicant: Intel Corporation
Inventor： Bernd Waidhas , Carlton Hanna , Stephen Morein , Lizabeth Keser , Georg Seidemann
IPC: H01L23/538 , H01L23/50 , H01L23/522
Abstract: Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a package substrate, having a surface, including a first conductive pathway electrically coupled to a power source; a first microelectronic component, having an active side electrically coupled to the surface of the package substrate and an opposing back side, surrounded by an insulating material; a second microelectronic component, having an active side electrically coupled to the surface of the package substrate and an opposing back side, surrounded by the insulating material and including a through-substrate via (TSV) electrically coupled to the first conductive pathway; and a redistribution layer (RDL), on the insulating material, including a second conductive pathway electrically coupling the TSV, the second surface of the second microelectronic component, and the second surface of the first microelectronic component.
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公开(公告)号：US12243856B2
公开(公告)日：2025-03-04
申请号：US18217000
申请日：2023-06-30
Applicant: Intel Corporation
Inventor： David O'Sullivan , Georg Seidemann , Richard Patten , Bernd Waidhas
Abstract: Embodiments include semiconductor packages and a method of forming the semiconductor packages. A semiconductor package includes a mold over and around a first die and a first via. The semiconductor package has a conductive pad of a first redistribution layer disposed on a top surface of the first die and/or a top surface of the mold. The semiconductor package includes a second die having a solder ball coupled to a die pad on a bottom surface of the second die, where the solder ball of the second die is coupled to the first redistribution layer. The first redistribution layer couples the second die to the first die, where the second die has a first edge and a second edge, and where the first edge is positioned within a footprint of the first die and the second edge is positioned outside the footprint of the first die.
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Patent Agency Ranking
公开(公告)号：US12211796B2
公开(公告)日：2025-01-28
申请号：US17355747
申请日：2021-06-23
Applicant: Intel Corporation
Inventor： Bernd Waidhas , Carlton Hanna , Stephen Morein , Lizabeth Keser , Georg Seidemann
IPC: H01L23/538 , H01L23/50 , H01L23/522
Abstract: Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a package substrate including a first conductive pathway electrically coupled to a power source; a first microelectronic component, embedded in an insulating material on the surface of the package substrate, including a through-substrate via (TSV) electrically coupled to the first conductive pathway; a second microelectronic component embedded in the insulating material; and a redistribution layer on the insulating material including a second conductive pathway electrically coupling the TSV, the second microelectronic component, and the first microelectronic component.
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公开(公告)号：US20240429221A1
公开(公告)日：2024-12-26
申请号：US18339685
申请日：2023-06-22
Applicant: Intel Corporation
Inventor： Bernd Waidhas , Thomas Wagner , Georg Seidemann , Nicolas Richaud , Manisha Dutta , Georgios Dogiamis , Harshit Dhakad , Michael Langenbuch
Abstract: Glass layers and capacitors for use with integrated circuit packages are disclosed. An example integrated circuit (IC) package includes a semiconductor die, a glass layer, and a capacitor electrically coupled to the semiconductor die, at least one side of the capacitor enclosed by the glass layer, the capacitor positioned closer to the glass layer than the semiconductor die is to the glass layer.
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公开(公告)号：US12125815B2
公开(公告)日：2024-10-22
申请号：US17131663
申请日：2020-12-22
Applicant: Intel Corporation
Inventor： Bernd Waidhas , Andreas Wolter , Georg Seidemann , Thomas Wagner
IPC: H01L23/31 , H01L23/00 , H01L23/538
CPC classification number: H01L24/20 , H01L23/3157 , H01L23/5386 , H01L24/06 , H01L24/13 , H01L2924/3511 , H01L2924/381
Abstract: Embodiments disclosed herein include electronic package and methods of forming such packages. In an embodiment, an electronic package comprises a mold layer and a first die embedded in the mold layer. In an embodiment, the first die comprises first pads at a first pitch and second pads at a second pitch. In an embodiment, the electronic package further comprises a second die embedded in the mold layer, where the second die comprises third pads at the first pitch and fourth pads at the second pitch. In an embodiment, a bridge die is embedded in the mold layer, and the bridge die electrically couples the second pads to the fourth pads.
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公开(公告)号：US11955395B2
公开(公告)日：2024-04-09
申请号：US17855674
申请日：2022-06-30
Applicant: Intel Corporation
Inventor： Lizabeth Keser , Bernd Waidhas , Thomas Ort , Thomas Wagner
IPC: H01L23/31 , H01L21/56 , H01L23/00 , H01L23/522 , H01L49/02
CPC classification number: H01L23/3114 , H01L21/568 , H01L23/5226 , H01L24/11 , H01L24/14 , H01L24/96 , H01L28/10 , H01L28/40 , H01L2224/02379 , H01L2924/19011
Abstract: A semiconductor device and method of including peripheral devices into a package is disclosed. In one example, a peripheral device includes a passive device such as a capacitor or an inductor. Examples are shown that include a peripheral device that is substantially the same thickness as a die or a die assembly. Examples are further shown that use this configuration in a fan out process to form semiconductor devices.
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30.发明授权公开(公告)号：US11877403B2
公开(公告)日：2024-01-16
申请号：US17486462
申请日：2021-09-27
Applicant: Intel Corporation
Inventor： Georg Seidemann , Sonja Koller , Bernd Waidhas
IPC: H05K3/34 , H01L23/498
CPC classification number: H05K3/3436 , H01L23/49816
Abstract: A printed wiring-board island relieves added complexity to a printed circuit board. The printed wiring-board island creates an island form factor in the printed circuit board. Coupling of a semiconductive device package to the printed wiring-board island includes a ball-grid array. The ball-grid array can at least partially penetrate the printed wiring-board island.
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