公开(公告)号：US10152370B2

公开(公告)日：2018-12-11

申请号：US14967210

申请日：2015-12-11

Applicant: INTEL CORPORATION

Inventor： Bill Nale

IPC: G06F12/00 ,  G06F11/07 ,  G11C29/02 ,  G06F12/0813 ,  G06F13/16 ,  G06F3/06 ,  G06F12/0802 ,  G06F12/02 ,  G06F13/42 ,  G11C7/22 ,  G11C11/406 ,  G11C5/14 ,  H04L9/08 ,  G11C5/04 ,  G11C7/10

Abstract: Provided are a method and apparatus for determining a timing adjustment of output to a host memory controller in a first memory module coupled to a host memory controller and a second memory module over a bus. A determination is made of a timing adjustment based on at least one component in at least one of the first memory module and the second memory module. A timing of output to the host memory controller is adjusted based on the determined timing adjustment to match a timing of output at the second memory module.

公开(公告)号：US09772799B2

公开(公告)日：2017-09-26

申请号：US14981307

申请日：2015-12-28

Applicant: INTEL CORPORATION

Inventor： Bill Nale

IPC: G06F12/00 ,  G06F3/06 ,  G11C7/10 ,  G11C7/22 ,  G11C8/18

CPC classification number: G06F3/0659 ,  G06F3/061 ,  G06F3/0673 ,  G11C7/109 ,  G11C7/22 ,  G11C8/18 ,  G11C2207/105

Abstract: In some embodiments a controller includes a memory activate pin, one or more combined memory command/address signal pins, and a selection circuit adapted to select in response to the memory activate pin as each of the one or more combined memory command/address signal pins either a memory command signal or a memory address signal. Other embodiments are described and claimed.

公开(公告)号：US20160179610A1

公开(公告)日：2016-06-23

申请号：US14578413

申请日：2014-12-20

Applicant: Intel Corporation

Inventor： Brian S. Morris ,  Bill Nale ,  Robert G. Blankenship ,  Eric L. Hendrickson

IPC: G06F11/08 ,  G06F11/16

CPC classification number: G06F11/08 ,  G06F11/1625 ,  G06F11/1654 ,  G06F11/167 ,  G06F13/00 ,  H04L1/00 ,  H04L1/0061 ,  H04L1/0082 ,  H04L1/1838 ,  H04L2001/0097

Abstract: Data is sent from a memory buffer device to a host device over a link. An error in the data is determined. A read response cancellation signal is sent to the host device to indicate the error to the host device, where the read response cancellation signal is to be sent subsequent to the data being sent from the memory buffer device to the host device.

Abstract translation: 数据通过链路从内存缓冲设备发送到主机设备。 确定数据中的错误。 读取响应消除信号被发送到主机设备以向主机设备指示错误，其中在将数据从存储器缓冲器件发送到主机设备之后要发送读取响应消除信号。

公开(公告)号：US12164373B2

公开(公告)日：2024-12-10

申请号：US17339754

申请日：2021-06-04

Applicant: Intel Corporation

Inventor： Bill Nale ,  Kuljit S. Bains ,  Lawrence Blankenbeckler ,  Ronald Anderson ,  Jongwon Lee

IPC: G06F11/00 ,  G06F11/10 ,  G11C11/406 ,  G11C11/4096

Abstract: A memory chip is described. The memory chip includes storage cells along a row of the memory chip's storage cell array to store a count value of the row's activations and error correction code (ECC) information to protect the count value. The memory chip includes ECC read logic circuitry to correct an error in the count value. The memory chip includes a comparator to compare the count value against a threshold. The memory chip includes circuitry to increment the count value if the count value is deemed not to have reached the threshold and ECC write logic circuitry to determine new ECC information for the incremented count value, and write driver circuitry to write the incremented count value and the new ECC information into the storage cells. The memory chip includes circuitry to cause the row to be refreshed if the count value is deemed to have reached the threshold.

公开(公告)号：US11990172B2

公开(公告)日：2024-05-21

申请号：US18213231

申请日：2023-06-22

Applicant: Intel Corporation

Inventor： Bill Nale ,  Christopher E. Cox

IPC: G11C11/406 ,  G06F3/06 ,  G11C11/4096

CPC classification number: G11C11/40611 ,  G06F3/0619 ,  G06F3/0659 ,  G06F3/0673 ,  G11C11/4096 ,  G11C11/40618

Abstract: A memory device with internal row hammer mitigation couples to a memory controller. The memory controller or host can assist with row hammer mitigation by sending additional refresh cycles or refresh commands. In response to an extra refresh command the memory device can perform refresh for row hammer mitigation instead of refresh for standard data integrity. The memory controller can keep track of the number of activate commands sent to the memory device, and in response to a threshold number of activate commands, the memory controller sends the additional refresh command. With the extra refresh command the memory device can refresh the potential victim rows of a potential aggressor row, instead of simply refreshing a row that has not been accessed for a period of time.

公开(公告)号：US11790976B2

公开(公告)日：2023-10-17

申请号：US17666452

申请日：2022-02-07

Applicant: Intel Corporation

Inventor： Christopher E. Cox ,  Bill Nale

IPC: G11C7/10 ,  G11C11/406 ,  G06F3/06 ,  G11C11/4093 ,  G11C29/02

CPC classification number: G11C11/40615 ,  G06F3/0659 ,  G11C7/10 ,  G11C7/1057 ,  G11C11/4093 ,  G11C29/021 ,  G11C29/022 ,  G11C29/028 ,  G11C29/023 ,  G11C2207/2254

Abstract: A memory device is described. The memory device includes logic circuitry to perform calibrations of resistive network terminations and data drivers of the memory device while the memory device is within a self refresh mode.

公开(公告)号：US10997096B2

公开(公告)日：2021-05-04

申请号：US15987854

申请日：2018-05-23

Applicant: Intel Corporation

Inventor： Tonia G. Morris ,  Bill Nale

IPC: G06F13/16 ,  G06F3/06 ,  G06F9/30 ,  G06F12/02 ,  G06F1/26

Abstract: A memory subsystem enables per device addressability (PDA) to target configuration commands to one of multiple memory devices that share a select line or buffer devices that share an enable line. The system includes a host and multiple memory devices that can be coupled over a command bus and a data bus. The devices include a configuration or mode register to store a value to indicate whether PDA enumeration is enabled. When enabled, the host can provide an enumeration identifier (ID) command via the command bus with a signal via the data bus to assign an enumeration ID. After assignment of the enumeration ID, the host can send PDA commands via the command bus with the enumeration ID, without a signal on the data bus. Devices only process PDA commands that match their assigned enumeration ID, enabling the setting of device-specific configuration settings without needing to use the data bus on every PDA command.

公开(公告)号：US10795755B2

公开(公告)日：2020-10-06

申请号：US15080577

申请日：2016-03-24

Applicant: INTEL CORPORATION

Inventor： Bill Nale ,  Jonathan C. Jasper ,  Murugasamy K. Nachimuthu ,  Jun Zhu ,  Tuan M. Quach

IPC: G06F12/00 ,  G06F11/07 ,  G11C29/02 ,  G06F12/0813 ,  G06F13/16 ,  G06F3/06 ,  G06F12/0802 ,  G06F12/02 ,  G06F13/42 ,  G11C7/10 ,  G11C7/22 ,  G11C11/406 ,  G11C5/14 ,  H04L9/08 ,  G11C5/04

Abstract: Provided are a method and apparatus for performing error handling operations using error signals A first error signal is asserted on an error pin on a bus to signal to a host memory controller that error handling operations are being performed by a memory module controller in response to detecting an error. Error handling operations are performed to return the bus to an initial state in response to detecting the error. A second error signal is asserted on the error pin on the bus to signal that error handling operations have completed and the bus is returned to the initial state.

公开(公告)号：US10339072B2

公开(公告)日：2019-07-02

申请号：US15089455

申请日：2016-04-01

Applicant: Intel Corporation

Inventor： Bill Nale ,  Pete D Vogt

IPC: G06F13/16 ,  G06F3/06 ,  G06F13/40 ,  G11C5/06 ,  G11C7/10 ,  G11C5/04

Abstract: A system with memory includes a repeater architecture where the memory connects to a host with one bandwidth, and a repeater extends a channel with a lower bandwidth. A memory circuit includes a first group of memory devices coupled point-to-point to a host device via a first group of read signal lines. The memory circuit includes a second group of memory devices coupled point-to-point to the first group of memory devices second group of read signal lines to extend the memory channel to the second group of memory devices. The second group of read signal lines has fewer read signal lines than the first group. The memory circuit includes a repeater to share read bandwidth between the first and second groups of memory devices, with up to a portion of the bandwidth for reads to the second group of memory devices, and at least an amount equal to the bandwidth less the portion for reads to the first group of memory devices. The repeater or buffer may accumulate data read from the second group of memory devices or a second memory module and burst the accumulated data to the host device with the first bandwidth.

公开(公告)号：US09904591B2

公开(公告)日：2018-02-27

申请号：US14918428

申请日：2015-10-20

Applicant: Intel Corporation

Inventor： John B. Halbert ,  Kuljit S. Bains ,  Debaleena Das ,  Bill Nale

IPC: G11C29/00 ,  G06F11/10 ,  G06F11/07 ,  G06F13/00 ,  G06F11/08

CPC classification number: G06F11/1004 ,  G06F11/073 ,  G06F11/076 ,  G06F11/0772 ,  G06F11/08 ,  G06F13/00

Abstract: Techniques and mechanisms to provide selective access to data error information by a memory controller. In an embodiment, a memory device stores a first value representing a baseline number of data errors determined prior to operation of the memory device with the memory controller. Error detection logic of the memory device determines a current count of data errors, and calculates a second value representing a difference between the count of data errors and the baseline number of data errors. The memory device provides the second value to the memory controller, which is unable to identify that the second value is a relative error count. In another embodiment, the memory controller is restricted from retrieving the baseline number of data errors.