公开(公告)号：US12147698B2

公开(公告)日：2024-11-19

申请号：US17214770

申请日：2021-03-26

Applicant: Intel Corporation

Inventor： Bill Nale ,  George Vergis

IPC: G06F3/00 ,  G06F3/06

Abstract: An apparatus is described. The apparatus includes a register clock driver (RCD) semiconductor chip having first inputs to receive first command and address (CA) signals from a first sub-channel and first outputs to drive first and second instances of the CA information that are decoded from the first CA signals. The RCD semiconductor chip has second inputs to receive second command and address (CA) signals from a second sub-channel. The RCD semiconductor chip has a multiplexer having a first input channel to receive the first CA signals and a second input channel to receive the second CA signals. The RCD semiconductor chip has second outputs to drive third and fourth instances of the first CA information or first and second instances of the second CA information that are decoded from the second CA signals depending on which of the first and second input channels of the multiplexer is selected.

公开(公告)号：US11276453B2

公开(公告)日：2022-03-15

申请号：US16879583

申请日：2020-05-20

Applicant: Intel Corporation

Inventor： Christopher E. Cox ,  Bill Nale

IPC: G11C7/10 ,  G11C11/406 ,  G06F3/06 ,  G11C11/4093 ,  G11C29/02

Abstract: A memory device is described. The memory device includes logic circuitry to perform calibrations of resistive network terminations and data drivers of the memory device while the memory device is within a self refresh mode.

公开(公告)号：US10950288B2

公开(公告)日：2021-03-16

申请号：US16370578

申请日：2019-03-29

Applicant: Intel Corporation

Inventor： Bill Nale ,  Christopher E. Cox

IPC: G11C11/406 ,  G11C11/4096 ,  G06F3/06

Abstract: A memory device with internal row hammer mitigation couples to a memory controller. The memory controller or host can assist with row hammer mitigation by sending additional refresh cycles or refresh commands. In response to an extra refresh command the memory device can perform refresh for row hammer mitigation instead of refresh for standard data integrity. The memory controller can keep track of the number of activate commands sent to the memory device, and in response to a threshold number of activate commands, the memory controller sends the additional refresh command. With the extra refresh command the memory device can refresh the potential victim rows of a potential aggressor row, instead of simply refreshing a row that has not been accessed for a period of time.

公开(公告)号：US10810141B2

公开(公告)日：2020-10-20

申请号：US15720659

申请日：2017-09-29

Applicant: Intel Corporation

Inventor： Mahesh S. Natu ,  Murugasamy K. Nachimuthu ,  Bill Nale

IPC: G06F12/14 ,  G06F12/084 ,  G06F9/50 ,  G06F9/4401

Abstract: Systems, apparatuses and methods may provide for technology that conducts a comparison between an identified capability of a memory device and memory usage rules associated with a processor. The memory usage rules are to identify allowed memory accesses by the processor. The technology further limits access by the processor to the memory device based upon the comparison.

公开(公告)号：US10783028B2

公开(公告)日：2020-09-22

申请号：US14995145

申请日：2016-01-13

Applicant: INTEL CORPORATION

Inventor： Bill Nale

IPC: G06F12/00 ,  G06F11/07 ,  G11C29/02 ,  G06F12/0813 ,  G06F13/16 ,  G06F3/06 ,  G06F12/0802 ,  G06F12/02 ,  G06F13/42 ,  G11C7/10 ,  G11C7/22 ,  G11C11/406 ,  G11C5/14 ,  H04L9/08 ,  G11C5/04

Abstract: Provided are a method and apparatus for setting high address bits in a memory module. A memory module controller in the memory module, having pins to communicate on a bus, determines whether high address bits are available for the memory module, uses a predetermined value for at least one high address bit with addresses communicated from a host memory controller in response to determine that the high address bits are not available to address a first address space in the memory module, and uses values communicated from the host memory controller on at least one of the pins used for the at least one high address bit in response to determine that the high address bits are available to address a second address space, wherein the second address space is larger than the first address space.

公开(公告)号：US10360096B2

公开(公告)日：2019-07-23

申请号：US15462185

申请日：2017-03-17

Applicant: Intel Corporation

Inventor： Brian S. Morris ,  Bill Nale ,  Robert G. Blankenship ,  Eric L. Hendrickson

IPC: G06F11/00 ,  G06F11/08 ,  G06F11/16 ,  G06F13/00 ,  H04L1/00 ,  H04L1/18

Abstract: Data is sent from a memory buffer device to a host device over a link. An error in the data is determined. A read response cancellation signal is sent to the host device to indicate the error to the host device, where the read response cancellation signal is to be sent subsequent to the data being sent from the memory buffer device to the host device.

公开(公告)号：US10198379B2

公开(公告)日：2019-02-05

申请号：US15669197

申请日：2017-08-04

Applicant: Intel Corporation

Inventor： Brian S. Morris ,  Bill Nale ,  Robert G. Blankenship ,  Jeffrey C. Swanson

IPC: G06F13/28 ,  G06F13/16 ,  G06F13/38 ,  G06F13/42

Abstract: A sequence of read returns are to be sent to a host device over a transactional buffered memory interface, where the sequence includes at least a first read return to a first read request and a second read return to a second read request. A tracker identifier of the second read return is encoded in the first read return and the first read return is sent with the tracker identifier of the second read return to the host device. The second read return is sent to the host device after the first read return is sent.

公开(公告)号：US20170278562A1

公开(公告)日：2017-09-28

申请号：US15197424

申请日：2016-06-29

Applicant: Intel Corporation

Inventor： Bill Nale

IPC: G11C11/406 ,  G11C7/10

CPC classification number: G11C11/40618 ,  G11C5/04 ,  G11C7/1045 ,  G11C7/1057 ,  G11C7/1072 ,  G11C7/20

Abstract: Examples may include techniques to use chip select signals for a dual in-line memory module (DIMM). In some examples, the chip select signals are used with either a first encoding scheme for clock enable (CKE) functionality or a second encoding scheme for on-die termination (ODT) functionality to enable memory devices on the DIMM to be accessed or controlled according to commands received with the chip select signals.

公开(公告)号：US20160179718A1

公开(公告)日：2016-06-23

申请号：US14578407

申请日：2014-12-20

Applicant: Intel Corporation

Inventor： Brian S. Morris ,  Bill Nale ,  Robert G. Blankenship ,  Jeffrey C. Swanson

IPC: G06F13/28 ,  G06F13/42

CPC classification number: G06F13/28 ,  G06F13/1642 ,  G06F13/382 ,  G06F13/4221

Abstract: A sequence of read returns are to be sent to a host device over a transactional buffered memory interface, where the sequence includes at least a first read return to a first read request and a second read return to a second read request. A tracker identifier of the second read return is encoded in the first read return and the first read return is sent with the tracker identifier of the second read return to the host device. The second read return is sent to the host device after the first read return is sent.

Abstract translation: 读取返回序列将通过事务缓冲存储器接口发送到主机设备，其中序列至少包括对第一读取请求的第一读取返回和第二读取返回到第二读取请求。 在第一读取返回中编码第二读取返回的跟踪器标识符，并且将第一读取返回与第二读取返回的跟踪器标识符一起发送到主机设备。 在发送第一次读取返回后，第二个读取返回被发送到主机设备。

公开(公告)号：US12190979B2

公开(公告)日：2025-01-07

申请号：US18373658

申请日：2023-09-27

Applicant: Intel Corporation

Inventor： Bill Nale

IPC: G11C29/44 ,  G06F11/30 ,  G06F11/32 ,  G11C29/00 ,  G11C29/02 ,  G11C29/46

Abstract: Self-test and repair of memory cells is performed in a memory integrated circuit by two separate processes initiated by a memory controller communicatively coupled to the memory integrated circuit. To ensure that the repair process is completed in the event of an unexpected power failure, a first process is initiated by the memory controller to perform a memory Built-in Self Test (mBIST) in the memory integrated circuit and a second process is initiated by the memory controller after the mBIST has completed to perform repair of faulty memory cells detected during the MBIST process. The memory controller does not initiate the repair process if a power failure has been detected. In addition, a repair time associated with the repair process is selected such that the repair time is sufficient to complete the repair process while power is stable, if a power failure occurs after the repair process has been started.