公开(公告)号：US09952801B2

公开(公告)日：2018-04-24

申请号：US14752554

申请日：2015-06-26

Applicant: Intel Corporation

Inventor： Raj K. Ramanujan ,  Jun Zhu ,  Mohamed Arafa ,  Woojong Han ,  Jordan A. Horwich

IPC: G06F12/02 ,  G06F3/06 ,  G06F12/1027 ,  G06F12/1009 ,  G06F12/0866

CPC classification number: G06F3/0649 ,  G06F3/0616 ,  G06F3/0685 ,  G06F12/0246 ,  G06F12/0866 ,  G06F12/1009 ,  G06F12/1027 ,  G06F2212/202 ,  G06F2212/214 ,  G06F2212/22 ,  G06F2212/7211

Abstract: Embodiments are generally directed to accelerated address indirection table lookup for wear-leveled non-volatile memory. A embodiment of a memory device includes nonvolatile memory; a memory controller; and address indirection logic to provide address indirection for the nonvolatile memory, of the address indirection logic to maintain an address indirection table (AIT) in the nonvolatile memory, the AIT including a plurality of levels, and copy at least a portion of the AIT to a second memory, the second memory having less latency than the first memory.

公开(公告)号：US10747605B2

公开(公告)日：2020-08-18

申请号：US15058126

申请日：2016-03-01

Applicant: INTEL CORPORATION

Inventor： Bill Nale ,  Jun Zhu ,  Tuan M. Quach

IPC: G06F12/00 ,  G06F11/07 ,  G11C29/02 ,  G06F12/0813 ,  G06F13/16 ,  G06F3/06 ,  G06F12/0802 ,  G06F12/02 ,  G06F13/42 ,  G11C7/10 ,  G11C7/22 ,  G11C11/406 ,  G11C5/14 ,  H04L9/08 ,  G11C5/04

Abstract: Provided are a method and apparatus for providing a host memory controller write credits for write commands. A host memory controller coupled to a memory module over a bus determines whether a read data packet returned from the memory module indicates at least one write credit and increments a write credit counter in response to determining that the read data packet indicates at least one write credit.

公开(公告)号：US10579462B2

公开(公告)日：2020-03-03

申请号：US15058129

申请日：2016-03-01

Applicant: INTEL CORPORATION

Inventor： Bill Nale ,  Jun Zhu ,  Tuan M. Quach

IPC: G06F12/00 ,  G06F11/07 ,  G11C29/02 ,  G06F12/0813 ,  G06F13/16 ,  G06F3/06 ,  G06F12/0802 ,  G06F12/02 ,  G06F13/42 ,  G11C7/10 ,  G11C7/22 ,  G11C11/406 ,  G11C5/14 ,  H04L9/08 ,  G11C5/04

Abstract: Provided are a method and apparatus for using an error signal to indicate a write request error and write request acceptance performing error handling operations using error signals. A memory module controller detects a write error for a write request in a memory module and asserts an error signal on a bus to a host memory controller in response to detecting the write error.

公开(公告)号：US10198306B2

公开(公告)日：2019-02-05

申请号：US14967230

申请日：2015-12-11

Applicant: INTEL CORPORATION

Inventor： Bill Nale ,  Jun Zhu ,  Tuan M. Quach

IPC: G06F12/00 ,  G06F11/07 ,  G11C29/02 ,  G06F12/0813 ,  G06F13/16 ,  G06F3/06 ,  G06F12/0802 ,  G06F12/02 ,  G06F13/42 ,  G11C7/10 ,  G11C7/22 ,  G11C11/406 ,  G11C5/14 ,  H04L9/08 ,  G11C5/04

Abstract: Provided are a method and apparatus for a memory module to accept a command in multiple parts. A first half of a command is placed on a bus for a memory module in a first clock cycle. A chip select signal is placed on the bus for the memory module for the first half of the command. A second half of the command is placed on the bus in a second clock cycle following the first clock cycle, wherein the memory module accepts the second half of the command a delay interval from accepting the first half of the command.

公开(公告)号：US20160378396A1

公开(公告)日：2016-12-29

申请号：US14752554

申请日：2015-06-26

Applicant: Intel Corporation

Inventor： Raj K. Ramanujan ,  Jun Zhu ,  Mohamed Arafa ,  Woojong Han ,  Jordan A. Horwich

IPC: G06F3/06 ,  G06F12/10 ,  G06F12/08

CPC classification number: G06F3/0649 ,  G06F3/0616 ,  G06F3/0685 ,  G06F12/0246 ,  G06F12/0866 ,  G06F12/1009 ,  G06F12/1027 ,  G06F2212/202 ,  G06F2212/214 ,  G06F2212/22 ,  G06F2212/7211

Abstract: Embodiments are generally directed to accelerated address indirection table lookup for wear-leveled non-volatile memory. A embodiment of a memory device includes nonvolatile memory; a memory controller; and address indirection logic to provide address indirection for the nonvolatile memory, of the address indirection logic to maintain an address indirection table (AIT) in the nonvolatile memory, the AIT including a plurality of levels, and copy at least a portion of the AIT to a second memory, the second memory having less latency than the first memory.

Abstract translation: 实施例通常涉及用于磨损级别的非易失性存储器的加速地址间接表查找。 存储器件的实施例包括非易失性存储器; 内存控制器 以及地址间接逻辑以提供所述非易失性存储器的地址间接，所述地址间接逻辑用于在所述非易失性存储器中维护地址间接表（AIT），所述AIT包括多个级别，并将所述AIT的至少一部分复制到 第二存储器，第二存储器具有比第一存储器更少的延迟。

公开(公告)号：US10795755B2

公开(公告)日：2020-10-06

申请号：US15080577

申请日：2016-03-24

Applicant: INTEL CORPORATION

Inventor： Bill Nale ,  Jonathan C. Jasper ,  Murugasamy K. Nachimuthu ,  Jun Zhu ,  Tuan M. Quach

IPC: G06F12/00 ,  G06F11/07 ,  G11C29/02 ,  G06F12/0813 ,  G06F13/16 ,  G06F3/06 ,  G06F12/0802 ,  G06F12/02 ,  G06F13/42 ,  G11C7/10 ,  G11C7/22 ,  G11C11/406 ,  G11C5/14 ,  H04L9/08 ,  G11C5/04

Abstract: Provided are a method and apparatus for performing error handling operations using error signals A first error signal is asserted on an error pin on a bus to signal to a host memory controller that error handling operations are being performed by a memory module controller in response to detecting an error. Error handling operations are performed to return the bus to an initial state in response to detecting the error. A second error signal is asserted on the error pin on the bus to signal that error handling operations have completed and the bus is returned to the initial state.

公开(公告)号：US20150149735A1

公开(公告)日：2015-05-28

申请号：US13977653

申请日：2013-03-15

Applicant: Intel Corporation

Inventor： Bill Nale ,  Murugasamy K. Nachimuthu ,  Jun Zhu ,  Tuan M. Quach

IPC: G06F13/16 ,  G06F12/08

CPC classification number: G06F11/0793 ,  G06F3/0604 ,  G06F3/061 ,  G06F3/0629 ,  G06F3/0638 ,  G06F3/0673 ,  G06F3/0683 ,  G06F11/0727 ,  G06F11/0751 ,  G06F11/0772 ,  G06F11/079 ,  G06F12/023 ,  G06F12/0802 ,  G06F12/0813 ,  G06F13/1663 ,  G06F13/1678 ,  G06F13/1689 ,  G06F13/1694 ,  G06F13/4234 ,  G06F13/4243 ,  G06F13/4282 ,  G06F2212/1044 ,  G06F2212/2532 ,  G06F2212/60 ,  G11C5/04 ,  G11C5/148 ,  G11C7/1003 ,  G11C7/1063 ,  G11C7/1072 ,  G11C7/222 ,  G11C11/40618 ,  G11C29/023 ,  G11C29/028 ,  H04L9/0869

Abstract: Provided is a device for use in a memory module coupled to a host memory controller over a bus, comprising memory module control logic to generate a request signal to a host memory controller having a pulse width greater than or equal to a minimum pulse width, wherein the minimum pulse width comprises a number of clock cycles needed to guarantee that the host memory controller detects the request signal, and wherein the pulse width of the request signal indicates at least one function in addition to the request signal to the host memory controller.

Abstract translation: 提供了一种用于通过总线耦合到主机存储器控制器的存储器模块中的装置，包括存储器模块控制逻辑，以产生具有大于或等于最小脉冲宽度的脉冲宽度的主机存储器控制器的请求信号，其中 所述最小脉冲宽度包括保证所述主机存储器控制器检测到所述请求信号所需的多个时钟周期，并且其中所述请求信号的脉冲宽度除了对所述主机存储器控制器的所述请求信号之外还指示至少一个功能。

公开(公告)号：US09990246B2

公开(公告)日：2018-06-05

申请号：US13977653

申请日：2013-03-15

Applicant: Intel Corporation

Inventor： Bill Nale ,  Murugasamy K. Nachimuthu ,  Jun Zhu ,  Tuan M. Quach

IPC: G06F12/00 ,  G06F11/07 ,  G11C29/02 ,  G06F12/0813 ,  G06F13/16 ,  G06F3/06 ,  G06F12/0802 ,  G06F12/02 ,  G06F13/42 ,  G11C7/22 ,  G11C11/406 ,  G11C5/14 ,  H04L9/08 ,  G11C5/04 ,  G11C7/10

CPC classification number: G06F11/0793 ,  G06F3/0604 ,  G06F3/061 ,  G06F3/0629 ,  G06F3/0638 ,  G06F3/0673 ,  G06F3/0683 ,  G06F11/0727 ,  G06F11/0751 ,  G06F11/0772 ,  G06F11/079 ,  G06F12/023 ,  G06F12/0802 ,  G06F12/0813 ,  G06F13/1663 ,  G06F13/1678 ,  G06F13/1689 ,  G06F13/1694 ,  G06F13/4234 ,  G06F13/4243 ,  G06F13/4282 ,  G06F2212/1044 ,  G06F2212/2532 ,  G06F2212/60 ,  G11C5/04 ,  G11C5/148 ,  G11C7/1003 ,  G11C7/1063 ,  G11C7/1072 ,  G11C7/222 ,  G11C11/40618 ,  G11C29/023 ,  G11C29/028 ,  H04L9/0869

Abstract: Provided is a device for use in a memory module coupled to a host memory controller over a bus, comprising memory module control logic to generate a request signal to a host memory controller having a pulse width greater than or equal to a minimum pulse width, wherein the minimum pulse width comprises a number of clock cycles needed to guarantee that the host memory controller detects the request signal, and wherein the pulse width of the request signal indicates at least one function in addition to the request signal to the host memory controller.