公开(公告)号：US20190341384A1

公开(公告)日：2019-11-07

申请号：US16473699

申请日：2017-03-15

Applicant: Intel Corporation

Inventor： Aaron D. Lilak ,  Patrick Theofanis ,  Cory E. Weber ,  Stephen M. Cea ,  Rishabh Mehandru

IPC: H01L27/105 ,  H01L27/11556 ,  H01L27/11582 ,  H01L29/78 ,  H01L21/32

Abstract: An integrated circuit structure is provided which comprises: a stack of source regions of a stack of transistors and a stack of drain regions of the stack of transistors; and a gate stack that forms gate regions for the stack of transistors, wherein the gate stack comprises traces of a first polymer of a block copolymer, the block copolymer comprising the first polymer and a second polymer.

公开(公告)号：US20190267448A1

公开(公告)日：2019-08-29

申请号：US16412305

申请日：2019-05-14

Applicant: Intel Corporation

Inventor： Cory E. Weber ,  Aaron D. Lilak ,  Szuya S. Liao ,  Aaron A. Budrevich

IPC: H01L29/06 ,  H01L29/78 ,  H01L21/223 ,  H01L21/225 ,  H01L29/66 ,  H01L21/265 ,  H01L21/266 ,  H01L21/3115

Abstract: Methods and structures formed thereby are described relating to the doping non-planar fin structures. An embodiment of a structure includes a substrate, wherein the substrate comprises silicon, a fin on the substrate comprising a first portion and a second portion; and a dopant species, wherein the first portion comprises a first dopant species concentration, and the second portion comprises a second dopant species concentration, wherein the first dopant species concentration is substantially less than the second dopant species concentration.

公开(公告)号：US20170222052A1

公开(公告)日：2017-08-03

申请号：US15489423

申请日：2017-04-17

Applicant: Intel Corporation

Inventor： Cory E. Weber ,  Mark Y. Liu ,  Anand S. Murthy ,  Hemant V. Deshpande ,  Daniel B. Aubertine

IPC: H01L29/78 ,  H01L29/08 ,  H01L29/66 ,  H01L29/16 ,  H01L29/417 ,  H01L21/265 ,  H01L29/165

CPC classification number: H01L29/7848 ,  H01L21/26506 ,  H01L29/0847 ,  H01L29/16 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/165 ,  H01L29/41783 ,  H01L29/66477 ,  H01L29/66628 ,  H01L29/78 ,  H01L29/7847 ,  H01L29/7849

Abstract: A device is provided. The device includes a transistor formed on a semiconductor substrate, the transistor having a conduction channel. The device includes at least one edge dislocation formed adjacent to the conduction channel on the semiconductor substrate. The device also includes at least one free surface introduced above the conduction channel and the at least one edge dislocation.

公开(公告)号：US12191349B2

公开(公告)日：2025-01-07

申请号：US16649287

申请日：2017-12-15

Applicant: INTEL CORPORATION

Inventor： Dipanjan Basu ,  Cory E. Weber ,  Justin R. Weber ,  Sean T. Ma ,  Harold W. Kennel ,  Seung Hoon Sung ,  Glenn A. Glass ,  Jack T. Kavalieros ,  Tahir Ghani

IPC: H01L29/06 ,  H01L27/088 ,  H01L29/08 ,  H01L29/161 ,  H01L29/201 ,  H01L29/205 ,  H01L29/423 ,  H01L29/775 ,  H01L29/78 ,  H01L29/786 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/66

Abstract: Material systems for source region, drain region, and a semiconductor body of transistor devices in which the semiconductor body is electrically insulated from an underlying substrate are selected to reduce or eliminate a band to band tunneling (“BTBT”) effect between different energetic bands of the semiconductor body and one or both of the source region and the drain region. This can be accomplished by selecting a material for the semiconductor body with a band gap that is larger than a band gap for material(s) selected for the source region and/or drain region.

公开(公告)号：US11522072B2

公开(公告)日：2022-12-06

申请号：US17080458

申请日：2020-10-26

Applicant: Intel Corporation

Inventor： Rishabh Mehandru ,  Patrick Morrow ,  Ranjith Kumar ,  Cory E. Weber ,  Seiyon Kim ,  Stephen M. Cea ,  Tahir Ghani

IPC: H01L29/45 ,  H01L29/16 ,  H01L29/66 ,  H01L29/78 ,  H01L21/822 ,  H01L21/8238 ,  H01L27/06 ,  H01L27/11 ,  H01L21/8234 ,  H01L21/84 ,  H01L27/108 ,  H01L27/12 ,  H01L29/778

Abstract: Vertical integration schemes and circuit elements architectures for area scaling of semiconductor devices are described. In an example, an inverter structure includes a semiconductor fin separated vertically into an upper region and a lower region. A first plurality of gate structures is included for controlling the upper region of the semiconductor fin. A second plurality of gate structures is included for controlling the lower region of the semiconductor fin. The second plurality of gate structures has a conductivity type opposite the conductivity type of the first plurality of gate structures.

公开(公告)号：US20200279910A1

公开(公告)日：2020-09-03

申请号：US16649287

申请日：2017-12-15

Applicant: INTEL CORPORATION

Inventor： Dipanjan Basu ,  Cory E. Weber ,  Justin R. Weber ,  Sean T. Ma ,  Harold W. Kennel ,  Seung Hoon Sung ,  Glenn A. Glass ,  Jack T. Kavalieros ,  Tahir Ghani

IPC: H01L29/06 ,  H01L29/66 ,  H01L29/786 ,  H01L29/78 ,  H01L29/205 ,  H01L29/161 ,  H01L29/775

Abstract: Material systems for source region, drain region, and a semiconductor body of transistor devices in which the semiconductor body is electrically insulated from an underlying substrate are selected to reduce or eliminate a band to band tunneling (“BTBT”) effect between different energetic bands of the semiconductor body and one or both of the source region and the drain region. This can be accomplished by selecting a material for the semiconductor body with a band gap that is larger than a band gap for material(s) selected for the source region and/or drain region.

公开(公告)号：US20200013861A1

公开(公告)日：2020-01-09

申请号：US16489660

申请日：2017-03-31

Applicant: Intel Corporation

Inventor： Abhishek A. Sharma ,  Van H. Le ,  Gilbert W. Dewey ,  Shriram Shivaraman ,  Tahir Ghani ,  Jack T. Kavalieros ,  Cory E. Weber

IPC: H01L29/24 ,  H01L27/108 ,  H01L29/786

Abstract: Substrates, assemblies, and techniques for a backend transistor, where the backend transistor includes a gate, a semiconductor oxide, a source metal and a drain metal, and an insulator between the source metal and the gate and between the drain metal and the gate. The insulator can allow for tunneling between the source metal and/or the drain metal and the semiconductor oxide.

公开(公告)号：US09660078B2

公开(公告)日：2017-05-23

申请号：US14951840

申请日：2015-11-25

Applicant: Intel Corporation

Inventor： Cory E. Weber ,  Mark Y. Liu ,  Anand Murthy ,  Hemant Deshpande ,  Daniel B. Aubertine

IPC: H01L29/15 ,  H01L31/0312 ,  H01L29/78 ,  H01L21/265 ,  H01L29/417 ,  H01L29/66 ,  H01L29/16 ,  H01L29/08 ,  H01L29/161 ,  H01L29/165

CPC classification number: H01L29/7848 ,  H01L21/26506 ,  H01L29/0847 ,  H01L29/16 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/165 ,  H01L29/41783 ,  H01L29/66477 ,  H01L29/66628 ,  H01L29/78 ,  H01L29/7847 ,  H01L29/7849

Abstract: A device is provided. The device includes a transistor formed on a semiconductor substrate, the transistor having a conduction channel. The device includes at least one edge dislocation formed adjacent to the conduction channel on the semiconductor substrate. The device also includes at least one free surface introduced above the conduction channel and the at least one edge dislocation.

公开(公告)号：US20150155384A1

公开(公告)日：2015-06-04

申请号：US14582391

申请日：2014-12-24

Applicant: Intel Corporation

Inventor： Cory E. Weber ,  Mark Y. Liu ,  Anand Murthy ,  Hemant Deshpande ,  Daniel B. Aubertine

IPC: H01L29/78 ,  H01L29/16 ,  H01L29/417

CPC classification number: H01L29/7848 ,  H01L21/26506 ,  H01L29/0847 ,  H01L29/16 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/165 ,  H01L29/41783 ,  H01L29/66477 ,  H01L29/66628 ,  H01L29/78 ,  H01L29/7847 ,  H01L29/7849

Abstract: A device is provided. The device includes a transistor formed on a semiconductor substrate, the transistor having a conduction channel. The device includes at least one edge dislocation formed adjacent to the conduction channel on the semiconductor substrate. The device also includes at least one free surface introduced above the conduction channel and the at least one edge dislocation.

Abstract translation: 提供了一种设备。 该器件包括形成在半导体衬底上的晶体管，该晶体管具有导通沟道。 该器件包括与半导体衬底上的导电沟道相邻形成的至少一个边缘位错。 该装置还包括在导电通道之上引入的至少一个自由表面和至少一个边缘错位。