公开(公告)号：US20240211310A1

公开(公告)日：2024-06-27

申请号：US18598837

申请日：2024-03-07

Applicant: Intel Corporation

Inventor： Francesc Guim Bernat ,  Kshitij A. Doshi ,  Daniel Rivas Barragan ,  Alejandro Duran Gonzalez ,  Harald Servat

IPC: G06F9/50 ,  H04L45/745 ,  H04L61/103 ,  H04L67/1004 ,  H04L67/1097 ,  H04L67/51 ,  H04L67/566 ,  H04W8/22

CPC classification number: G06F9/5005 ,  G06F9/5016 ,  G06F9/5022 ,  H04L67/1097 ,  H04L67/51 ,  H04W8/22 ,  G06F2209/463 ,  H04L45/745 ,  H04L61/103 ,  H04L67/1004 ,  H04L67/566

Abstract: Technologies for dynamically sharing remote resources include a computing node that sends a resource request for remote resources to a remote computing node in response to a determination that additional resources are required by the computing node. The computing node configures a mapping of a local address space of the computing node to the remote resources of the remote computing node in response to sending the resource request. In response to generating an access to the local address, the computing node identifies the remote computing node based on the local address with the mapping of the local address space to the remote resources of the remote computing node and performs a resource access operation with the remote computing node over a network fabric. The remote computing node may be identified with system address decoders of a caching agent and a host fabric interface. Other embodiments are described and claimed.

公开(公告)号：US20230047886A1

公开(公告)日：2023-02-16

申请号：US17978788

申请日：2022-11-01

Applicant: Intel Corporation

Inventor： Francesc Guim Bernat ,  Kshitij A. Doshi ,  Daniel Rivas Barragan ,  Alejandro Duran Gonzalez ,  Harald Servat

IPC: G06F9/50 ,  H04W8/22 ,  H04L67/1097 ,  H04L67/51

Abstract: Technologies for dynamically sharing remote resources include a computing node that sends a resource request for remote resources to a remote computing node in response to a determination that additional resources are required by the computing node. The computing node configures a mapping of a local address space of the computing node to the remote resources of the remote computing node in response to sending the resource request. In response to generating an access to the local address, the computing node identifies the remote computing node based on the local address with the mapping of the local address space to the remote resources of the remote computing node and performs a resource access operation with the remote computing node over a network fabric. The remote computing node may be identified with system address decoders of a caching agent and a host fabric interface. Other embodiments are described and claimed.

公开(公告)号：US11444866B2

公开(公告)日：2022-09-13

申请号：US15655864

申请日：2017-07-20

Applicant: INTEL CORPORATION

Inventor： Daniel Rivas Barragan ,  Francesc Guim Bernat ,  Susanne M. Balle ,  John Chun Kwok Leung ,  Suraj Prabhakaran ,  Murugasamy K. Nachimuthu ,  Slawomir Putyrski

IPC: G06F15/173 ,  H04L43/16 ,  G06F16/22 ,  G06F16/23 ,  H04L41/0896 ,  H04L43/0876 ,  H04L47/80 ,  H04Q9/00 ,  H04L41/12 ,  H04L67/10 ,  H04L41/5025 ,  H04L67/1031 ,  H04L41/0816 ,  H04L67/00 ,  H04L43/0852 ,  H04L43/0894 ,  H04L41/5009 ,  H04L41/5054 ,  H04L41/16 ,  H04L47/722

Abstract: Techniques for managing static and dynamic partitions in software-defined infrastructures (SDI) are described. An SDI manager component may include one or more processor circuits to access one or more resources. The SDI manager component may include a partition manager to create one or more partitions using the one or more resources, the one or more partitions each including a plurality of nodes of a similar resource type. The SDI manager may generate an update to a pre-composed partition table, stored within a non-transitory computer-readable storage medium, including the created one or more partitions, and receive a request from an orchestrator for a node. The SDI manager may select one of the created one or more partitions to the orchestrator based upon the pre-composed partition table, and identify the selected partition to the orchestrator. Other embodiments are described and claimed.

公开(公告)号：US10992556B2

公开(公告)日：2021-04-27

申请号：US15613944

申请日：2017-06-05

Applicant: Intel Corporation

Inventor： Francesc Guim Bernat ,  Karthik Kumar ,  Susanne M. Balle ,  Daniel Rivas Barragan ,  Rahul Khanna

IPC: H04L12/26 ,  H04L29/08 ,  H04L12/70 ,  G06F16/9535

Abstract: Particular embodiments described herein provide for a network element that can be configured to receive a request related to one or more disaggregated resources, link the one or more disaggregated resources to a local counter, receive performance related data from each of the one or more disaggregated resources, and store the performance related data in the local counter. In an example, the one or more disaggregated resources comprise a software defined infrastructure composite node

公开(公告)号：US20190095122A1

公开(公告)日：2019-03-28

申请号：US15717963

申请日：2017-09-28

Applicant: Intel Corporation

Inventor： Francesc Guim Bernat ,  Kshitij Doshi ,  Daniel Rivas Barragan ,  Federico Ardanaz ,  Suraj Prabhakaran

IPC: G06F3/06

Abstract: According to various aspects, a computing system may include one or more first memories of a first memory type and one or more second memories of a second memory type different from the first memory type and a memory controller. The memory controller may be configured to receive telemetry data associated with at least one of the one or more first memories and the one or more second memories, execute a data transfer between the one or more first memories and the one or more second memories in a first operation mode of the memory controller, suspend a data transfer between the one or more first memories and the one or more second memories in a second operation mode of the memory controller, and switch between the first operation mode and the second operation mode based on the telemetry data.

公开(公告)号：US20190004862A1

公开(公告)日：2019-01-03

申请号：US15637003

申请日：2017-06-29

Applicant: Intel Corporation

Inventor： Francesc Guim Bernat ,  Kshitij A. Doshi ,  Andrew J. Herdrich ,  Edwin Verplanke ,  Daniel Rivas Barragan

IPC: G06F9/50

Abstract: Technologies for managing quality of service of a platform interconnect include a compute device. The compute device includes one or more processors, one or more resources capable of being utilized by the one or more processors, and a platform interconnect to facilitate communication of messages between the one or more processors and the one or more resources. The compute device is to obtain class of service data for one or more workloads to be executed by the compute device. The class of service data is indicative of a capacity of one or more of the resources to be utilized in the execution of each corresponding workload. The compute device is also to execute the one or more workloads and manage the amount of traffic transmitted through the platform interconnect for each corresponding workload as a function of the class of service data as the one or more workloads are executed.

公开(公告)号：US20180351836A1

公开(公告)日：2018-12-06

申请号：US15613944

申请日：2017-06-05

Applicant: Intel Corporation

Inventor： Francesc Guim Bernat ,  Karthik Kumar ,  Susanne M. Balle ,  Daniel Rivas Barragan ,  Rahul Khanna

IPC: H04L12/26 ,  H04L29/08 ,  H04L12/24

Abstract: Particular embodiments described herein provide for a network element that can be configured to receive a request related to one or more disaggregated resources, link the one or more disaggregated resources to a local counter, receive performance related data from each of the one or more disaggregated resources, and store the performance related data in the local counter. In an example, the one or more disaggregated resources comprise a software defined infrastructure composite node

公开(公告)号：US20180077270A1

公开(公告)日：2018-03-15

申请号：US15260613

申请日：2016-09-09

Applicant: Intel Corporation

Inventor： Francesc Guim Bernat ,  Karthik Kumar ,  Thomas Willhalm ,  Raj K. Ramanujan ,  Daniel Rivas Barragan

IPC: H04L29/08 ,  H04L12/50 ,  H04L1/16

CPC classification number: H04L69/324 ,  G06F15/173 ,  H04L1/1642 ,  H04L12/50 ,  H04L49/00

Abstract: Technologies for using fabric supported sequencers in fabric architectures includes a network switch communicatively coupled to a plurality of computing nodes. The network switch is configured to receive an sequencer access message from one of the plurality of computing nodes that includes an identifier of a sequencing counter corresponding to a sequencer session and one or more operation parameters. The network switch is additionally configured to perform an operation on a value associated with the identifier of the sequencing counter as a function of the one or more operation parameters, increment the identifier of the sequencing counter, and associate a result of the operation with the incremented identifier of the sequencing counter. The network switch is further configured to transmit an acknowledgment of successful access to the computing node that includes the result of the operation and the incremented identifier of the sequencing counter. Other embodiments are described herein.

公开(公告)号：US20180077226A1

公开(公告)日：2018-03-15

申请号：US15260638

申请日：2016-09-09

Applicant: Intel Corporation

Inventor： Francesc Guim Bernat ,  Kshitij A. Doshi ,  Daniel Rivas Barragan ,  Alejandro Duran Gonzalez

IPC: H04L29/08 ,  H04L12/933

CPC classification number: H04L49/15 ,  H04L29/10

Abstract: Technologies for performing switch-based collective operations in a fabric architecture include a network switch communicatively coupled to a plurality of computing nodes. The network switch is configured to identify sub-operations of a collective operation of a collective operation request received from one of the computing nodes and identify a plurality of operands for each of the sub-operations. The network switch is additionally configured to request a value for each of the operands from a corresponding target computing node at which the respective value is stored, determine a result of the collective operation as a function of the requested operand values, and transmit the result to the requesting computing node. Other embodiments are described herein.

公开(公告)号：US11870662B2

公开(公告)日：2024-01-09

申请号：US17690642

申请日：2022-03-09

Applicant: INTEL CORPORATION

Inventor： Francesc Guim Bernat ,  Kshitij A. Doshi ,  Daniel Rivas Barragan ,  Mark A. Schmisseur ,  Steen Larsen

IPC: G06F15/173 ,  H04L41/5025 ,  H04L43/0817 ,  H04L43/16 ,  H04L41/0896

CPC classification number: H04L41/5025 ,  H04L41/0896 ,  H04L43/0817 ,  H04L43/16

Abstract: Embodiments may be generally directed to techniques to cause communication of a registration request between a first end-point and a second end-point of an end-to-end path, the registration request to establish resource load monitoring for one or more resources of the end-to-end path, receive one or more acknowledgements indicating resource loads for each of the one or more resources of the end-to-end path, at least one of the acknowledgements to indicate a resource of the one or more resources is not meeting a threshold requirement for the end-to-end path, and perform an action for communication traffic utilizing the one or more resources based on the acknowledgement.