公开(公告)号：US11276760B2

公开(公告)日：2022-03-15

申请号：US16435301

申请日：2019-06-07

Applicant: Intel Corporation

Inventor： Gopinath Bhimarasetti ,  Walid M. Hafez ,  Joodong Park ,  Weimin Han ,  Raymond E. Cotner ,  Chia-Hong Jan

IPC: H01L29/36 ,  H01L29/66 ,  H01L29/78 ,  H01L21/8234 ,  H01L27/088

Abstract: Non-planar semiconductor devices having omega-fins with doped sub-fin regions and methods of fabricating non-planar semiconductor devices having omega-fins with doped sub-fin regions are described. For example, a semiconductor device includes a plurality of semiconductor fins disposed above a semiconductor substrate, each semiconductor fin having a sub-fin portion below a protruding portion, the sub-fin portion narrower than the protruding portion. A solid state dopant source layer is disposed above the semiconductor substrate, conformal with the sub-fin region but not the protruding portion of each of the plurality of semiconductor fins. An isolation layer is disposed above the solid state dopant source layer and between the sub-fin regions of the plurality of semiconductor fins. A gate stack is disposed above the isolation layer and conformal with the protruding portions of each of the plurality of semiconductor fins.

公开(公告)号：US11063137B2

公开(公告)日：2021-07-13

申请号：US16302698

申请日：2016-06-28

Applicant: Intel Corporation

Inventor： Jui-Yen Lin ,  Chen-Guan Lee ,  Joodong Park ,  Walid M. Hafez ,  Kun-Huan Shih

IPC: H01L29/78 ,  H01L29/66 ,  H01L21/8234 ,  H01L27/088 ,  H01L21/28 ,  H01L21/265

Abstract: An embodiment includes an apparatus comprising: a transistor including a source, a drain, and a gate that has first and second sidewalls; a first spacer on the first sidewall between the drain and the gate; a second spacer on the second sidewall between the source and the gate; and a third spacer on the first spacer. Other embodiments are described herein.

公开(公告)号：US10892261B2

公开(公告)日：2021-01-12

申请号：US16318107

申请日：2016-09-29

Applicant: Intel Corporation

Inventor： Walid M. Hafez ,  Roman W. Olac-Vaw ,  Joodong Park ,  Chen-Guan Lee ,  Chia-Hong Jan

IPC: H01L27/088 ,  H01L27/06 ,  H01L21/8234 ,  H01L49/02 ,  H01L29/66 ,  H01L29/78

Abstract: Metal resistors and self-aligned gate edge (SAGE) architectures having metal resistors are described. In an example, a semiconductor structure includes a plurality of semiconductor fins protruding through a trench isolation region above a substrate. A first gate structure is over a first of the plurality of semiconductor fins. A second gate structure is over a second of the plurality of semiconductor fins. A gate edge isolation structure is laterally between and in contact with the first gate structure and the second gate structure. The gate edge isolation structure is on the trench isolation region and extends above an uppermost surface of the first gate structure and the second gate structure. A metal layer is on the gate edge isolation structure and is electrically isolated from the first gate structure and the second gate structure.

公开(公告)号：US10355093B2

公开(公告)日：2019-07-16

申请号：US15122796

申请日：2014-06-26

Applicant: Intel Corporation

Inventor： Gopinath Bhimarasetti ,  Walid M. Hafez ,  Joodong Park ,  Weimin Han ,  Raymond E. Cotner ,  Chia-Hong Jan

IPC: H01L29/36 ,  H01L29/66 ,  H01L29/78 ,  H01L21/8234 ,  H01L27/088

Abstract: Non-planar semiconductor devices having omega-fins with doped sub-fin regions and methods of fabricating non-planar semiconductor devices having omega-fins with doped sub-fin regions are described. For example, a semiconductor device includes a plurality of semiconductor fins disposed above a semiconductor substrate, each semiconductor fin having a sub-fin portion below a protruding portion, the sub-fin portion narrower than the protruding portion. A solid state dopant source layer is disposed above the semiconductor substrate, conformal with the sub-fin region but not the protruding portion of each of the plurality of semiconductor fins. An isolation layer is disposed above the solid state dopant source layer and between the sub-fin regions of the plurality of semiconductor fins. A gate stack is disposed above the isolation layer and conformal with the protruding portions of each of the plurality of semiconductor fins.

公开(公告)号：US10340220B2

公开(公告)日：2019-07-02

申请号：US15748608

申请日：2015-08-26

Applicant: Intel Corporation

Inventor： Chen-Guan Lee ,  Vadym Kapinus ,  Pei-Chi Liu ,  Joodong Park ,  Walid M. Hafez ,  Chia-Hong Jan

IPC: H01L23/522 ,  H01L27/06 ,  H01L49/02 ,  H01L29/78 ,  H01L21/86 ,  H01L29/786

Abstract: IC device structures including a lateral compound resistor disposed over a surface of a substrate, and fabrication techniques to form such a resistor in conjunction with fabrication of a transistor. Rather than being stacked vertically, a compound resistive trace may include a plurality of resistive materials arranged laterally over a substrate. Along a resistive trace length, a first resistive material is in contact with a sidewall of a second resistive material. A portion of a first resistive material along a centerline of the resistive trace may be replaced with a second resistive material so that the second resistive material is embedded within the first resistive material.

公开(公告)号：US20190123170A1

公开(公告)日：2019-04-25

申请号：US16302698

申请日：2016-06-28

Applicant: Intel Corporation

Inventor： Jui-Yen Lin ,  Chen-Guan Lee ,  Joodong Park ,  Walid M. Hafez ,  Kun-Huan Shih

IPC: H01L29/66 ,  H01L21/265 ,  H01L21/8234 ,  H01L27/088

Abstract: An embodiment includes an apparatus comprising: a transistor including a source, a drain, and a gate that has first and second sidewalls; a first spacer on the first sidewall between the drain and the gate; a second spacer on the second sidewall between the source and the gate; and a third spacer on the first spacer. Other embodiments are described herein.

公开(公告)号：US09972642B2

公开(公告)日：2018-05-15

申请号：US15784318

申请日：2017-10-16

Applicant: Intel Corporation

Inventor： Walid M. Hafez ,  Jeng-Ya D. Yeh ,  Curtis Tsai ,  Joodong Park ,  Chia-Hong Jan ,  Gopinath Bhimarasetti

IPC: H01L27/12 ,  H01L29/51 ,  H01L29/66 ,  H01L21/8234 ,  H01L21/84 ,  H01L21/28 ,  H01L21/02 ,  H01L29/423

CPC classification number: H01L27/1211 ,  H01L21/02164 ,  H01L21/0228 ,  H01L21/02532 ,  H01L21/02598 ,  H01L21/28158 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823462 ,  H01L21/823468 ,  H01L21/845 ,  H01L29/42356 ,  H01L29/51 ,  H01L29/513 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/6681

Abstract: High voltage three-dimensional devices having dielectric liners and methods of forming high voltage three-dimensional devices having dielectric liners are described. For example, a semiconductor structure includes a first fin active region and a second fin active region disposed above a substrate. A first gate structure is disposed above a top surface of, and along sidewalls of, the first fin active region. The first gate structure includes a first gate dielectric, a first gate electrode, and first spacers. The first gate dielectric is composed of a first dielectric layer disposed on the first fin active region and along sidewalls of the first spacers, and a second, different, dielectric layer disposed on the first dielectric layer and along sidewalls of the first spacers. The semiconductor structure also includes a second gate structure disposed above a top surface of, and along sidewalls of, the second fin active region. The second gate structure includes a second gate dielectric, a second gate electrode, and second spacers. The second gate dielectric is composed of the second dielectric layer disposed on the second fin active region and along sidewalls of the second spacers.

公开(公告)号：US09748252B2

公开(公告)日：2017-08-29

申请号：US14880814

申请日：2015-10-12

Applicant: INTEL CORPORATION

Inventor： Walid M. Hafez ,  Chia-Hong Jan ,  Curtis Tsai ,  Joodong Park ,  Jeng-Ya D. Yeh

IPC: H01L27/112 ,  H01L23/525 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/78

CPC classification number: H01L27/11206 ,  H01L21/823821 ,  H01L23/5252 ,  H01L27/0924 ,  H01L29/7853 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Techniques for providing non-volatile antifuse memory elements and other antifuse links are disclosed herein. In some embodiments, the antifuse memory elements are configured with non-planar topology such as FinFET topology. In some such embodiments, the fin topology can be manipulated and used to effectively promote lower breakdown voltage transistors, by creating enhanced-emission sites which are suitable for use in lower voltage non-volatile antifuse memory elements. In one example embodiment, a semiconductor antifuse device is provided that includes a non-planar diffusion area having a fin configured with a tapered portion, a dielectric isolation layer on the fin including the tapered portion, and a gate material on the dielectric isolation layer. The tapered portion of the fin may be formed, for instance, by oxidation, etching, and/or ablation, and in some cases includes a base region and a thinned region, and the thinned region is at least 50% thinner than the base region.

公开(公告)号：US20170162693A1

公开(公告)日：2017-06-08

申请号：US15323726

申请日：2014-08-05

Applicant: INTEL CORPORATION

Inventor： Gopinath Bhimarasetti ,  Walid Hafez ,  Joodong Park ,  Weimin Han ,  Raymond Cotner

IPC: H01L29/78 ,  H01L21/762 ,  H01L29/66 ,  H01L29/423

CPC classification number: H01L29/7846 ,  H01L21/02238 ,  H01L21/02255 ,  H01L21/76202 ,  H01L21/823431 ,  H01L29/42376 ,  H01L29/66795 ,  H01L29/785

Abstract: Non-planar transistor devices which include oxide isolation structures formed in semiconductor bodies thereof through the formation of an oxidizing catalyst layer on the semiconductor bodies followed by an oxidation process. In one embodiment, the semiconductor bodies may be formed from silicon-containing materials and the oxidizing catalyst layer may comprise aluminum oxide, wherein oxidizing the semiconductor body to form an oxide isolation zone forms a semiconductor body first portion and a semiconductor body second portion with the isolation zone substantially electrically separating the semiconductor body first portion and the semiconductor body second portion.

公开(公告)号：US11251201B2

公开(公告)日：2022-02-15

申请号：US17072850

申请日：2020-10-16

Applicant: Intel Corporation

Inventor： Walid M. Hafez ,  Jeng-Ya D. Yeh ,  Curtis Tsai ,  Joodong Park ,  Chia-Hong Jan ,  Gopinath Bhimarasetti

IPC: H01L27/12 ,  H01L21/8234 ,  H01L21/84 ,  H01L29/66 ,  H01L21/02 ,  H01L21/28 ,  H01L29/423 ,  H01L29/51

Abstract: High voltage three-dimensional devices having dielectric liners and methods of forming high voltage three-dimensional devices having dielectric liners are described. For example, a semiconductor structure includes a first fin active region and a second fin active region disposed above a substrate. A first gate structure is disposed above a top surface of, and along sidewalls of, the first fin active region. The first gate structure includes a first gate dielectric, a first gate electrode, and first spacers. The first gate dielectric is composed of a first dielectric layer disposed on the first fin active region and along sidewalls of the first spacers, and a second, different, dielectric layer disposed on the first dielectric layer and along sidewalls of the first spacers. The semiconductor structure also includes a second gate structure disposed above a top surface of, and along sidewalls of, the second fin active region. The second gate structure includes a second gate dielectric, a second gate electrode, and second spacers. The second gate dielectric is composed of the second dielectric layer disposed on the second fin active region and along sidewalls of the second spacers.