公开(公告)号：US09477515B2

公开(公告)日：2016-10-25

申请号：US13956495

申请日：2013-08-01

Applicant: Intel Corporation

Inventor： Koichi Yamada ,  Landy Wang ,  Martin Taillefer ,  Arun Kishan ,  David Callahan ,  Jan Gray ,  Gad Sheaffer ,  Ali-Reza Adl-Tabatabai

IPC: G06F9/46 ,  G06F9/30 ,  G06F9/38

CPC classification number: G06F9/467 ,  G06F9/30076 ,  G06F9/3834 ,  G06F9/3836 ,  G06F9/3857 ,  G06F9/3861

Abstract: In one embodiment, the present invention includes a method for receiving control in a kernel mode via a ring transition from a user thread during execution of an unbounded transactional memory (UTM) transaction, updating a state of a transaction status register (TSR) associated with the user thread and storing the TSR with a context of the user thread, and later restoring the context during a transition from the kernel mode to the user thread. In this way, the UTM transaction may continue on resumption of the user thread. Other embodiments are described and claimed.

Abstract translation: 在一个实施例中，本发明包括一种用于在执行无界事务存储器（UTM）事务期间经由用户线程的环转移以内核模式接收控制的方法，更新与相关联的事务状态寄存器（TSR）相关联的事务状态寄存器（TSR）的状态 用户线程和用户线程的上下文存储TSR，然后在从内核模式到用户线程的转换期间恢复上下文。 以这种方式，UTM事务可以继续恢复用户线程。 描述和要求保护其他实施例。

公开(公告)号：US09405551B2

公开(公告)日：2016-08-02

申请号：US13795720

申请日：2013-03-12

Applicant: Intel Corporation

Inventor： Koichi Yamada ,  Palanivel Rajan Shanmugavelayutham ,  Scott D. Rodgers ,  Barry E. Huntley ,  James D. Beaney, Jr. ,  Boaz Tamir

IPC: G06F15/00 ,  G06F15/76 ,  G06F9/38 ,  G06F9/44 ,  G06F9/455

CPC classification number: G06F9/3885 ,  G06F9/44 ,  G06F9/45516 ,  G06F9/45533 ,  Y02D10/26 ,  Y02D10/28

Abstract: In an embodiment, a processor includes a binary translation (BT) container having code to generate a binary translation of a first code segment and to store the binary translation in a translation cache, a host entity logic to manage the BT container and to identify the first code segment, and protection logic to isolate the BT container from a software stack. In this way, the BT container is configured to be transparent to the software stack. Other embodiments are described and claimed.

Abstract translation: 在一个实施例中，处理器包括具有生成第一代码段的二进制转换和将二进制转换存储在转换高速缓存中的代码的二进制转换（BT）容器，用于管理BT容器的主机实体逻辑，并且识别 第一代码段和用于将BT容器与软件堆栈隔离的保护逻辑。 这样，BT容器被配置为对软件堆栈是透明的。 描述和要求保护其他实施例。

公开(公告)号：US09171159B2

公开(公告)日：2015-10-27

申请号：US13997411

申请日：2013-02-28

Applicant: Intel Corporation

Inventor： Palanivelrajan R. Shanmugavelayutham ,  Koichi Yamada ,  Ravi Sahita ,  Arvind Krishnaswamy

IPC: G06F21/62 ,  G06F21/56

CPC classification number: G06F21/566 ,  G06F21/54 ,  G06F21/56 ,  G06F21/567

Abstract: In an embodiment, a processor includes a binary translation engine to receive a code segment, to generate a binary translation of the code segment, and to store the binary translation in a translation cache, where the binary translation includes at least one policy check routine to be executed during execution of the binary translation on behalf of a security agent. Other embodiments are described and claimed.

Abstract translation: 在一个实施例中，处理器包括二进制翻译引擎，用于接收代码段，生成代码段的二进制翻译，以及将二进制翻译存储在翻译高速缓存中，其中二进制翻译包括至少一个策略检查程序 在代表安全代理的二进制翻译执行期间执行。 描述和要求保护其他实施例。

公开(公告)号：US09135435B2

公开(公告)日：2015-09-15

申请号：US13766233

申请日：2013-02-13

Applicant: Intel Corporation

Inventor： Ashish Venkat ,  Arvind Krishnaswamy ,  Koichi Yamada ,  Palanivelrajan Rajan Shanmugavelayutham

IPC: G06F21/00 ,  G06F21/52 ,  G06F21/79

CPC classification number: G06F21/52 ,  G06F21/79

Abstract: This disclosure is directed to binary translator driven program state relocation. In general, a device may protect vulnerable program functions by setting them as non-executable. If an attempt is made to execute a protected program function, the program may trap to a binary translator in the device that may be configured to relocate program state from what has already been established (e.g., on a stack register). Program state may include resources (e.g., memory locations) used by the program during the course of execution. The binary translator may then translate the program into an executable form based on the relocated program state, and may be executed accordingly. Intruding code that attempts to overcome normal program execution and implement hostile operations (e.g., based the program state that is reflected in the stack register) will not function as intended since the relocated program state will cause unexpected results.

Abstract translation: 本公开涉及二进制转换器驱动的程序状态重定位。 通常，设备可以通过将其设置为不可执行来保护易受攻击的程序功能。 如果尝试执行受保护的程序功能，程序可能陷入设备中的二进制翻译器，该二进制翻译器可被配置为将程序状态从已经建立的位置重新定位（例如，在堆栈寄存器上）。 程序状态可以包括程序在执行过程中使用的资源（例如，存储器位置）。 然后，二进制翻译器可以基于重新定位的程序状态将程序转换成可执行形式，并且可以相应地执行。 尝试克服正常程序执行和实施敌对操作（例如，基于反映在堆栈寄存器中的程序状态）的入侵代码将不会按预期运行，因为重新定位的程序状态将导致意外的结果。

公开(公告)号：US08762127B2

公开(公告)日：2014-06-24

申请号：US13785561

申请日：2013-03-05

Applicant: Intel Corporation

Inventor： Sebastian Winkel ,  Koichi Yamada ,  Suresh Srinivas ,  James E. Smith

IPC: G06F9/445 ,  G06F9/30 ,  G06F12/08

CPC classification number: G06F9/3017 ,  G06F9/455 ,  G06F12/0873 ,  G06F12/0875

Abstract: In one embodiment, a processor can operate in multiple modes, including a direct execution mode and an emulation execution mode. More specifically, the processor may operate in a partial emulation model in which source instruction set architecture (ISA) instructions are directly handled in the direct execution mode and translated code generated by an emulation engine is handled in the emulation execution mode. Embodiments may also provide for efficient transitions between the modes using information that can be stored in one or more storages of the processor and elsewhere in a system. Other embodiments are described and claimed.

Abstract translation: 在一个实施例中，处理器可以在多种模式下操作，包括直接执行模式和仿真执行模式。 更具体地，处理器可以在部分仿真模型中操作，其中以直接执行模式直接处理源指令集架构（ISA）指令，并且在仿真执行模式中处理由仿真引擎生成的转换代码。 实施例还可以使用可以存储在处理器的一个或多个存储器和系统中的其他地方的信息来提供模式之间的有效转换。 描述和要求保护其他实施例。

公开(公告)号：US11693691B2

公开(公告)日：2023-07-04

申请号：US17381521

申请日：2021-07-21

Applicant: Intel Corporation

Inventor： Rajesh M. Sankaran ,  Gilbert Neiger ,  Narayan Ranganathan ,  Stephen R. Van Doren ,  Joseph Nuzman ,  Niall D. McDonnell ,  Michael A. O'Hanlon ,  Lokpraveen B. Mosur ,  Tracy Garrett Drysdale ,  Eriko Nurvitadhi ,  Asit K. Mishra ,  Ganesh Venkatesh ,  Deborah T. Marr ,  Nicholas P. Carter ,  Jonathan D. Pearce ,  Edward T. Grochowski ,  Richard J. Greco ,  Robert Valentine ,  Jesus Corbal ,  Thomas D. Fletcher ,  Dennis R. Bradford ,  Dwight P. Manley ,  Mark J. Charney ,  Jeffrey J. Cook ,  Paul Caprioli ,  Koichi Yamada ,  Kent D. Glossop ,  David B. Sheffield

IPC: G06F9/48 ,  G06F9/30 ,  G06F9/38

CPC classification number: G06F9/48 ,  G06F9/3001 ,  G06F9/3004 ,  G06F9/30036 ,  G06F9/383

Abstract: Embodiments of systems, methods, and apparatuses for heterogeneous computing are described. In some embodiments, a hardware heterogeneous scheduler dispatches instructions for execution on one or more plurality of heterogeneous processing elements, the instructions corresponding to a code fragment to be processed by the one or more of the plurality of heterogeneous processing elements, wherein the instructions are native instructions to at least one of the one or more of the plurality of heterogeneous processing elements.

公开(公告)号：US11093277B2

公开(公告)日：2021-08-17

申请号：US16913265

申请日：2020-06-26

Applicant: Intel Corporation

Inventor： Rajesh M. Sankaran ,  Gilbert Neiger ,  Narayan Ranganathan ,  Stephen R. Van Doren ,  Joseph Nuzman ,  Niall D. McDonnell ,  Michael A. O'Hanlon ,  Lokpraveen B. Mosur ,  Tracy Garrett Drysdale ,  Eriko Nurvitadhi ,  Asit K. Mishra ,  Ganesh Venkatesh ,  Deborah T. Marr ,  Nicholas P. Carter ,  Jonathan D. Pearce ,  Edward T. Grochowski ,  Richard J. Greco ,  Robert Valentine ,  Jesus Corbal ,  Thomas D. Fletcher ,  Dennis R. Bradford ,  Dwight P. Manley ,  Mark J. Charney ,  Jeffrey J. Cook ,  Paul Caprioli ,  Koichi Yamada ,  Kent D. Glossop ,  David B. Sheffield

IPC: G06F9/48 ,  G06F9/30 ,  G06F9/38

Abstract: Embodiments of systems, methods, and apparatuses for heterogeneous computing are described. In some embodiments, a hardware heterogeneous scheduler dispatches instructions for execution on one or more plurality of heterogeneous processing elements, the instructions corresponding to a code fragment to be processed by the one or more of the plurality of heterogeneous processing elements, wherein the instructions are native instructions to at least one of the one or more of the plurality of heterogeneous processing elements.

公开(公告)号：US10114643B2

公开(公告)日：2018-10-30

申请号：US14129531

申请日：2013-05-23

Applicant: INTEL CORPORATION

Inventor： Koichi Yamada ,  Palanivelra Shanmugavelayutham ,  Arvind Krishnaswamy ,  Jason M. Agron ,  Jiwei Lu

IPC: G06F9/30 ,  G06F21/54 ,  G06F12/08 ,  G06F12/0875

Abstract: Various embodiments are generally directed to techniques to detect a return-oriented programming (ROP) attack by verifying target addresses of branch instructions during execution. An apparatus includes a processor component, and a comparison component for execution by the processor component to determine whether there is a matching valid target address for a target address of a branch instruction associated with a translated portion of a routine in a table comprising valid target addresses. Other embodiments are described and claimed.

公开(公告)号：US20180096147A1

公开(公告)日：2018-04-05

申请号：US15281825

申请日：2016-09-30

Applicant: Intel Corporation

Inventor： Tugrul Ince ,  Koichi Yamada ,  Ajay Harikumar ,  Alex Nayshtut

IPC: G06F21/56 ,  G06F11/36 ,  G06F21/52

CPC classification number: G06F21/566 ,  G06F11/3604 ,  G06F21/52 ,  G06F2221/033

Abstract: In one embodiment, a binary translator to perform binary translation of code is to: perform a first binary analysis of a first code block to determine whether a second control transfer instruction is included in the first code block, where the first code block includes a return target of a first control transfer instruction; perform a second binary analysis of a second code block to determine whether the second code block includes the first control transfer instruction, where the second code block includes a call target of the second control transfer instruction; and store an address pair associated with the first control transfer instruction in a whitelist if the second control transfer instruction is included in the first code block and the first control transfer instruction is included in the second code block. Other embodiments are described and claimed.

公开(公告)号：US20140282587A1

公开(公告)日：2014-09-18

申请号：US13997630

申请日：2013-03-13

Applicant: Intel Corporation

Inventor： Jason M. Argon ,  Koichi Yamada

IPC: G06F9/50

CPC classification number: G06F9/5027 ,  G06F1/3203 ,  G06F1/3206 ,  G06F1/329 ,  G06F9/505 ,  G06F9/5094 ,  G06F2209/5017 ,  Y02D10/22 ,  Y02D10/24

Abstract: Embodiments of techniques and systems associated with binary translation (BT) in computing systems are disclosed. In some embodiments, a BT task to be processed may be identified. The BT task may be associated with a set of code and may be identified during execution of the set of code on a first processing core of the computing device. The BT task may be queued in a queue accessible to a second processing core of the computing device, the second processing core being different from the first processing core. In response to a determination that the second processing core is in an idle state or has received an instruction through an operating system to enter an idle state, at least some of the BT task may be processed using the second processing core. Other embodiments may be described and/or claimed.

Abstract translation: 公开了与计算系统中的二进制翻译（BT）相关联的技术和系统的实施例。 在一些实施例中，可以识别待处理的BT任务。 BT任务可以与一组代码相关联，并且可以在计算设备的第一处理核心处的该代码集的执行期间被识别。 BT任务可以排队在计算设备的第二处理核心可访问的队列中，第二处理核心与第一处理核心不同。 响应于第二处理核心处于空闲状态或已经通过操作系统接收到进入空闲状态的指令的确定，可以使用第二处理核来处理BT任务中的至少一些。 可以描述和/或要求保护其他实施例。