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    Technologies for offloading and on-loading data for processor/coprocessor arrangements
    24.
    发明授权
    Technologies for offloading and on-loading data for processor/coprocessor arrangements 有权

    公开(公告)号：US10067805B2

    公开(公告)日：2018-09-04

    申请号：US15461635

    申请日：2017-03-17

    Applicant: Intel Corporation

    Inventor： Mingqiu Sun ,  Rajesh Poornachandran ,  Vincent J. Zimmer ,  Gopinatth Selvaraje ,  Uttam K. Sengupta

    IPC: G06F9/46 ,  G06F15/173 ,  G06F1/26 ,  G06F9/50 ,  G06N99/00

    Abstract: Technologies for transferring offloading or on-loading data or tasks between a processor and a coprocessor include a computing device having a processor and a sensor hub that includes a coprocessor. The coprocessor receives sensor data associated with one or more sensors and detects events associated with the sensor data. The coprocessor determines frequency, resource usage cost, and power state transition cost for the events. In response to an offloaded task request from the processor, the coprocessor determines an aggregate load value based on the frequency, resource usage cost, and power state transition cost, and determines whether to accept the offloaded task request based on the aggregate load value. The aggregate load value may be determined as an exponential moving average. The coprocessor may determine whether to accept the offloaded task request based on a principal component analysis of the events. Other embodiments are described and claimed.

    TECHNOLOGIES FOR OFFLOADING AND ON-LOADING DATA FOR PROCESSOR/COPROCESSOR ARRANGEMENTS
    25.
    发明申请
    TECHNOLOGIES FOR OFFLOADING AND ON-LOADING DATA FOR PROCESSOR/COPROCESSOR ARRANGEMENTS 审中-公开

    公开(公告)号：US20170185457A1

    公开(公告)日：2017-06-29

    申请号：US15461635

    申请日：2017-03-17

    Applicant: Intel Corporation

    Inventor： Mingqiu Sun ,  Rajesh Poornachandran ,  Vincent J. Zimmer ,  Gopinatth Selvaraje ,  Uttam K. Sengupta

    IPC: G06F9/50 ,  G06N99/00

    CPC classification number: G06F9/5094 ,  G06F9/5044 ,  G06F2209/509 ,  G06N99/005 ,  Y02D10/22

    Abstract: Technologies for transferring offloading or on-loading data or tasks between a processor and a coprocessor include a computing device having a processor and a sensor hub that includes a coprocessor. The coprocessor receives sensor data associated with one or more sensors and detects events associated with the sensor data. The coprocessor determines frequency, resource usage cost, and power state transition cost for the events. In response to an offloaded task request from the processor, the coprocessor determines an aggregate load value based on the frequency, resource usage cost, and power state transition cost, and determines whether to accept the offloaded task request based on the aggregate load value. The aggregate load value may be determined as an exponential moving average. The coprocessor may determine whether to accept the offloaded task request based on a principal component analysis of the events. Other embodiments are described and claimed.

    SECURE TRANSACTIONS WITH CONNECTED PERIPHERALS
    28.
    发明申请
    SECURE TRANSACTIONS WITH CONNECTED PERIPHERALS 审中-公开
    具有连接外围设备的安全交易

    公开(公告)号：US20160283928A1

    公开(公告)日：2016-09-29

    申请号：US14668715

    申请日：2015-03-25

    Applicant: Intel Corporation

    Inventor： Mingqiu Sun ,  Vincent J. Zimmer ,  Rajesh Poornachandran ,  Gopinatth Selvaraje

    IPC: G06Q20/20 ,  H04L29/06 ,  G06F21/60

    CPC classification number: G06Q20/204 ,  G06F21/606 ,  G06Q20/202 ,  G06Q20/4097 ,  H04L63/04 ,  H04L63/0428 ,  H04L63/101

    Abstract: A point-of-sale device (“POS”) is described to include a secure transaction tunnel generator (“STG”). The STG may generate secure tunnels between peripherals attached to the POS and remote network resources. The secure tunnel may be generated using a trusted execution environment (“TEE”) of the POS. The STG may be alerted to the need to generate the secure tunnel based on an alert from the peripheral. The STG may execute under a protected environment and may generate two ends of a secure transaction tunnel using the TEE. The STG may also check the peripheral against whitelists and/or blacklists to determine whether the peripheral is allowed or not disallowed to participate in secure transactions. By generating the secure tunnel, the STG may facilitate performance of transactions in such a way that sensitive information is not available to unsecured processes in the POS. Other embodiments may be described and/or claimed.

    Abstract translation: 销售点设备（“POS”）被描述为包括安全事务隧道生成器（“STG”）。 STG可以在连接到POS的外围设备和远程网络资源之间生成安全隧道。 可以使用POS的可信执行环境（“TEE”）生成安全隧道。 可以基于来自外围设备的警报，警告STG需要生成安全通道。 STG可以在受保护的环境下执行，并且可以使用TEE生成安全事务隧道的两端。 STG还可以检查外设是否有白名单和/或黑名单，以确定外设是否被允许或不允许参与安全事务。 通过生成安全隧道，STG可以以敏感信息不可用于POS中的不安全进程的方式促进事务的执行。 可以描述和/或要求保护其他实施例。

    Methods and apparatus to perform adaptive pre-fetch operations in managed runtime environments
    29.
    发明授权
    Methods and apparatus to perform adaptive pre-fetch operations in managed runtime environments 有权
    在受管运行环境中执行自适应预取操作的方法和装置

    公开(公告)号：US09280350B2

    公开(公告)日：2016-03-08

    申请号：US14586369

    申请日：2014-12-30

    Applicant: Intel Corporation

    Inventor： Mingqiu Sun

    IPC: G06F12/00 ,  G06F9/38 ,  G06F12/08

    CPC classification number: G06F9/3802 ,  G06F12/0862 ,  G06F2212/502

    Abstract: Methods and apparatus to perform adaptive pre-fetch operations in managed runtime environments are disclosed herein. An example disclosed method includes determining an object size associated with a pre-fetch operation; comparing the object size to a first one of a series of thresholds having increasing respective values; when the object size is less than the first one of the series of thresholds, pre-fetching a first amount of stored data assigned to the first one of the series of thresholds; and when the object size is greater than the first one of the plurality of thresholds, comparing the object size to a next one of the series of thresholds.

    Abstract translation: 本文公开了在被管理的运行时环境中执行自适应预取操作的方法和装置。 示例性公开的方法包括：确定与预取操作相关联的对象大小; 将对象大小与具有递增的相应值的一系列阈值中的第一个进行比较; 当所述对象大小小于所述一系列阈值中的第一个阈值时，预取分配给所述一系列阈值中的第一个阈值的第一数量的存储数据; 并且当所述对象大小大于所述多个阈值中的第一阈值时，将所述对象大小与所述一系列阈值中的下一个进行比较。

    HARDWARE ACCELERATION FOR INTERFACE TYPE CONVERSIONS
    30.
    发明申请
    HARDWARE ACCELERATION FOR INTERFACE TYPE CONVERSIONS 有权

    公开(公告)号：US20230026369A1

    公开(公告)日：2023-01-26

    申请号：US17957953

    申请日：2022-09-30

    Applicant: Intel Corporation

    Inventor： Mingqiu Sun

    IPC: G06F9/54

    Abstract: Technologies include an interface processor configured to be communicatively coupled to a memory and a first processor. The interface processor is to obtain, from a first module compiled from a first software language, first data having a first native type of the first software language. The interface processor is further to convert the first data into second data having a first interface type, convert the second data having the first interface type into third data having a second native type of a second software language, and provide the third data to a second module associated with the second software language. The first software language may be compiled to WebAssembly binary code. The second software language may also be compiled to WebAssembly binary code and may be different than the first software language.

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