公开(公告)号：US20210150328A1

公开(公告)日：2021-05-20

申请号：US17159312

申请日：2021-01-27

Applicant: Intel Corporation

Inventor： Deepak Dasalukunte ,  Richard Dorrance ,  Hechen Wang

IPC: G06N3/063 ,  G06N3/04 ,  H04L12/713 ,  H04L12/933

Abstract: Systems, methods, apparatuses, and computer-readable media. An analog router of a first supertile of a plurality of supertiles of a network on a chip (NoC) may receive a first analog output from a first compute-in-memory tile of a plurality of compute-in-memory tiles of the first supertile. The analog router may determine, based on a configuration of a neural network executing on the NoC, that a destination of the first analog output includes a second supertile of the plurality of supertiles. An analog-to-digital converter (ADC) of the analog router may convert the first analog output to a first digital output and transmit the first digital output to the second supertile via a communications bus of the NoC.

公开(公告)号：US20210034947A1

公开(公告)日：2021-02-04

申请号：US17075527

申请日：2020-10-20

Applicant: Intel Corporation

Inventor： Hechen Wang ,  Richard Dorrance ,  Deepak Dasalukunte ,  David Israel Gonzalez Aguirre

IPC: G06N3/04 ,  H03L7/089 ,  H03L7/099 ,  G06F1/06

Abstract: Methods, apparatus, systems, and articles of manufacture providing an improved Bayesian neural network and methods and apparatus to operate the same are disclosed. An example apparatus includes an oscillator to generate a first clock signal; a resistive element to adjust a slope of a rising edge of a second clock signal; a voltage sampler to generate a sample based on at least one of (a) a first voltage of the first clock signal when a second voltage of the second clock signal satisfies a threshold or (b) a third voltage of the second clock signal when a fourth voltage of the first clock signal satisfies the threshold; and a charge pump to adjust a weight based on the sample, the weight to adjust data in a model.

公开(公告)号：US20200238998A1

公开(公告)日：2020-07-30

申请号：US16830349

申请日：2020-03-26

Applicant: Intel Corporation

Inventor： Deepak Dasalukunte ,  Richard Dorrance ,  Ignacio Alvarez ,  Maria Soledad Elli ,  Sridhar Sharma ,  Satish Jha ,  Kathiravetpillai Sivanesan ,  S M Iftekharul Alam

IPC: B60W40/04 ,  B60W60/00 ,  G08G1/0969

Abstract: According to various embodiments, a method for operating a vehicle may include determining a vehicular area having traffic conditions or characteristics different from traffic conditions of a current or previous location of the vehicle; obtaining traffic and driving information for the determined vehicular region; changing or updating one or more of driving model parameters of a safety driving model during operation of the vehicle based on the obtained traffic and driving information; and controlling the vehicle to operate in accordance with the safety driving model using the one or more changed or updated driving model parameters. A vehicle may seamlessly update operational rules and/or handover of traffic and driving information for transitioning from one region to another.

公开(公告)号：US12254399B2

公开(公告)日：2025-03-18

申请号：US17159312

申请日：2021-01-27

Applicant: Intel Corporation

Inventor： Deepak Dasalukunte ,  Richard Dorrance ,  Hechen Wang

IPC: G06N3/065 ,  G06N3/047 ,  H04L45/586 ,  H04L49/109

Abstract: Systems, methods, apparatuses, and computer-readable media. An analog router of a first supertile of a plurality of supertiles of a network on a chip (NoC) may receive a first analog output from a first compute-in-memory tile of a plurality of compute-in-memory tiles of the first supertile. The analog router may determine, based on a configuration of a neural network executing on the NoC, that a destination of the first analog output includes a second supertile of the plurality of supertiles. An analog-to-digital converter (ADC) of the analog router may convert the first analog output to a first digital output and transmit the first digital output to the second supertile via a communications bus of the NoC.

公开(公告)号：US12131245B2

公开(公告)日：2024-10-29

申请号：US17075527

申请日：2020-10-20

Applicant: Intel Corporation

Inventor： Hechen Wang ,  Richard Dorrance ,  Deepak Dasalukunte ,  David Israel Gonzalez Aguirre

IPC: G06N3/04 ,  G06F1/06 ,  H03L7/089 ,  H03L7/099 ,  G11C11/412

CPC classification number: G06N3/04 ,  G06F1/06 ,  H03L7/0891 ,  H03L7/0995 ,  G11C11/412

Abstract: Methods, apparatus, systems, and articles of manufacture providing an improved Bayesian neural network and methods and apparatus to operate the same are disclosed. An example apparatus includes an oscillator to generate a first clock signal; a resistive element to adjust a slope of a rising edge of a second clock signal; a voltage sampler to generate a sample based on at least one of (a) a first voltage of the first clock signal when a second voltage of the second clock signal satisfies a threshold or (b) a third voltage of the second clock signal when a fourth voltage of the first clock signal satisfies the threshold; and a charge pump to adjust a weight based on the sample, the weight to adjust data in a model.

公开(公告)号：US20240045723A1

公开(公告)日：2024-02-08

申请号：US18477816

申请日：2023-09-29

Applicant: Intel Corporation

Inventor： Deepak Dasalukunte ,  Richard Dorrance ,  Renzhi Liu ,  Henchen Wang ,  Brent Carlton

IPC: G06F9/50 ,  G11C7/10

CPC classification number: G06F9/5033 ,  G06F9/5016 ,  G11C7/1012

Abstract: Systems, apparatuses and methods include technology that executes, with a compute-in-memory (CiM) element, first computations based on first data associated with a workload, and a storage of the first data, executes, with a compute-near memory (CnM) element, second computations based on second data associated with the workload and executes, with a compute-outside-of-memory (CoM) element, third computations based on third data associated with the workload. The technology further receives, with a multiplexer, processed data from a first element of the CiM element, the CnM element and the CoM element, and provides, with the multiplexer, the processed data to a second element of the CiM element, the CnM element and the CoM element.

公开(公告)号：US20230289066A1

公开(公告)日：2023-09-14

申请号：US18187950

申请日：2023-03-22

Applicant: Intel Corporation

Inventor： Renzhi Liu ,  Hechen Wang ,  Richard Dorrance ,  Deepak Dasalukunte ,  Brent Carlton

IPC: G06F3/06 ,  G06N3/0464 ,  G06F7/544

CPC classification number: G06F3/0613 ,  G06N3/0464 ,  G06F3/0659 ,  G06F3/0673 ,  G06F7/5443

Abstract: Systems, apparatuses and methods may provide for technology that includes a memory array to store multibit weight data and a capacitor ladder network to conduct multiply-accumulate (MAC) operations on first analog signals and multibit weight data, the capacitor ladder network further to output second analog signals based on the MAC operations, wherein the capacitor ladder network is external to the memory array. In one example, the capacitor ladder network includes a plurality of switches and the logic includes a controller to selectively activate the plurality of switches based on a data format of the multibit weight data.

公开(公告)号：US20230229504A1

公开(公告)日：2023-07-20

申请号：US17937248

申请日：2022-09-30

Applicant: Intel Corporation

Inventor： Renzhi Liu ,  Hechen Wang ,  Richard Dorrance ,  Deepak Dasalukunte ,  Brent Carlton

IPC: G06F9/50 ,  G06F7/544 ,  H03M1/18

CPC classification number: G06F9/5027 ,  G06F7/5443 ,  H03M1/18

Abstract: Systems, apparatuses and methods may provide for compute-in-memory (CiM) accelerator technology that includes a multiply-accumulate (MAC) computation stage, an analog amplifier stage coupled to an output of the MAC computation stage, and an analog to digital conversion (ADC) stage coupled to an output of the analog amplifier stage, wherein a gain setting of the analog amplifier stage modifies a quantization granularity of the ADC stage.

公开(公告)号：US20220209891A1

公开(公告)日：2022-06-30

申请号：US17134255

申请日：2020-12-25

Applicant: Intel Corporation

Inventor： Sundar Krishnamurthy ,  Lu Lu ,  Niranjan Mylarapa Gowda ,  Le Liang ,  Richard Dorrance ,  Deepak Dasalukunte ,  Arvind Merwaday

IPC: H04L1/00 ,  H04L27/38 ,  H04L25/02

Abstract: Bayesian Inference based communication receiver employs Markov-Chain Monte-Carlo (MCMC) sampling for performing several of the main receiver functionalities. The channel estimator estimates the multipath channel coefficients corresponding to a signal received with fading. The symbol demodulator demodulates the received signal according to a QAM constellation, so as to generate a demodulated signal, and estimate the transmitted symbols. The decoder reliably decodes the demodulated signals to generate an output bit sequence, factoring in redundancy induced at a certain code rate. A universal sampler may be configured to use MCMC sampling for generating estimates of channel coefficients, transmitted symbols or decoder bits, for aforementioned functionalities, respectively. The samples may then be used in one or more of the receiver tasks: channel estimation, signal demodulation, and decoding, which leads to a more scalable, reusable, power/area efficient receiver.