公开(公告)号：US20160187944A1

公开(公告)日：2016-06-30

申请号：US14583237

申请日：2014-12-26

Applicant: Intel Corporation

Inventor： Jonathan M. Eastep ,  Ilya Sharapov ,  Richard J. Greco ,  Steve S. Sylvester ,  David N. Lombard

IPC: G06F1/26 ,  G06F1/32

CPC classification number: G06F1/26 ,  G06F1/3203 ,  G06F1/324 ,  G06F9/5061 ,  G06F9/5094 ,  Y02D10/126 ,  Y02D10/22

Abstract: Systems and methods may provide a set of networked computational resources such as nodes that may be arranged in a hierarchy. A hierarchy of performance balancers receives performance samples from the computational resources beneath them and uses the performance samples to conduct a statistical analysis of variations in their performance. In one embodiment, the performance balancers steer power from faster resources to slower resources in order to enhance their performance, including in parallel processing.

Abstract translation: 系统和方法可以提供一组联网的计算资源，例如可以被布置在层次结构中的节点。 性能平衡器的层次结构从其下的计算资源接收性能样本，并使用性能样本对其性能的变化进行统计分析。 在一个实施例中，性能平衡器将功率从更快的资源转向较慢的资源，以便增强其性能，包括并行处理。

公开(公告)号：US11740673B2

公开(公告)日：2023-08-29

申请号：US17142149

申请日：2021-01-05

Applicant: Intel Corporation

Inventor： Jonathan M. Eastep ,  Richard J. Greco

IPC: G06F1/3203 ,  G06F9/48 ,  G06F9/50 ,  G06N20/00 ,  G06F1/329 ,  G06F9/38 ,  G06F9/52

CPC classification number: G06F1/3203 ,  G06F1/329 ,  G06F9/4881 ,  G06F9/4893 ,  G06F9/5094 ,  G06F9/38 ,  G06F9/50 ,  G06F9/505 ,  G06F9/522 ,  G06N20/00

Abstract: Methods and apparatus to provide holistic global performance and power management are described. In an embodiment, logic (e.g., coupled to each compute node of a plurality of compute nodes) causes determination of a policy for power and performance management across the plurality of compute nodes. The policy is coordinated across the plurality of compute nodes to manage a job to one or more objective functions, where the job includes a plurality of tasks that are to run concurrently on the plurality of compute nodes. Other embodiments are also disclosed and claimed.

公开(公告)号：US11693691B2

公开(公告)日：2023-07-04

申请号：US17381521

申请日：2021-07-21

Applicant: Intel Corporation

Inventor： Rajesh M. Sankaran ,  Gilbert Neiger ,  Narayan Ranganathan ,  Stephen R. Van Doren ,  Joseph Nuzman ,  Niall D. McDonnell ,  Michael A. O'Hanlon ,  Lokpraveen B. Mosur ,  Tracy Garrett Drysdale ,  Eriko Nurvitadhi ,  Asit K. Mishra ,  Ganesh Venkatesh ,  Deborah T. Marr ,  Nicholas P. Carter ,  Jonathan D. Pearce ,  Edward T. Grochowski ,  Richard J. Greco ,  Robert Valentine ,  Jesus Corbal ,  Thomas D. Fletcher ,  Dennis R. Bradford ,  Dwight P. Manley ,  Mark J. Charney ,  Jeffrey J. Cook ,  Paul Caprioli ,  Koichi Yamada ,  Kent D. Glossop ,  David B. Sheffield

IPC: G06F9/48 ,  G06F9/30 ,  G06F9/38

CPC classification number: G06F9/48 ,  G06F9/3001 ,  G06F9/3004 ,  G06F9/30036 ,  G06F9/383

Abstract: Embodiments of systems, methods, and apparatuses for heterogeneous computing are described. In some embodiments, a hardware heterogeneous scheduler dispatches instructions for execution on one or more plurality of heterogeneous processing elements, the instructions corresponding to a code fragment to be processed by the one or more of the plurality of heterogeneous processing elements, wherein the instructions are native instructions to at least one of the one or more of the plurality of heterogeneous processing elements.

公开(公告)号：US11093277B2

公开(公告)日：2021-08-17

申请号：US16913265

申请日：2020-06-26

Applicant: Intel Corporation

Inventor： Rajesh M. Sankaran ,  Gilbert Neiger ,  Narayan Ranganathan ,  Stephen R. Van Doren ,  Joseph Nuzman ,  Niall D. McDonnell ,  Michael A. O'Hanlon ,  Lokpraveen B. Mosur ,  Tracy Garrett Drysdale ,  Eriko Nurvitadhi ,  Asit K. Mishra ,  Ganesh Venkatesh ,  Deborah T. Marr ,  Nicholas P. Carter ,  Jonathan D. Pearce ,  Edward T. Grochowski ,  Richard J. Greco ,  Robert Valentine ,  Jesus Corbal ,  Thomas D. Fletcher ,  Dennis R. Bradford ,  Dwight P. Manley ,  Mark J. Charney ,  Jeffrey J. Cook ,  Paul Caprioli ,  Koichi Yamada ,  Kent D. Glossop ,  David B. Sheffield

IPC: G06F9/48 ,  G06F9/30 ,  G06F9/38

Abstract: Embodiments of systems, methods, and apparatuses for heterogeneous computing are described. In some embodiments, a hardware heterogeneous scheduler dispatches instructions for execution on one or more plurality of heterogeneous processing elements, the instructions corresponding to a code fragment to be processed by the one or more of the plurality of heterogeneous processing elements, wherein the instructions are native instructions to at least one of the one or more of the plurality of heterogeneous processing elements.

公开(公告)号：US10521002B2

公开(公告)日：2019-12-31

申请号：US15788195

申请日：2017-10-19

Applicant: INTEL CORPORATION

Inventor： Jonathan M. Eastep ,  Rohit Banerjee ,  Richard J. Greco ,  Ilya Sharapov ,  David N. Lombard ,  Hari K. Nagpal

IPC: G06F1/32 ,  G06F1/3234 ,  G06F1/3206

Abstract: Apparatus, systems, and methods provide dynamic spatial power steering among a plurality of power domains in the computer system on a per phase basis of a particular application. Dynamic spatial power steering may include, for example, determining a plurality of phases corresponding to an application comprising tasks for execution on a processing node. determining a spatial power distribution between a plurality of power domains on the processing node based on a performance metric for each phase, monitoring the application to detect a current phase, and applying the spatial power distribution correspond to the current phase to the plurality of power domains.

公开(公告)号：US10346300B2

公开(公告)日：2019-07-09

申请号：US15628811

申请日：2017-06-21

Applicant: Intel Corporation

Inventor： Avinash Sodani ,  Robert J. Kyanko ,  Richard J. Greco ,  Andreas Kleen ,  Milind B. Girkar ,  Christopher M. Cantalupo

IPC: G06F12/00 ,  G06F13/00 ,  G06F12/06 ,  G06F12/02

Abstract: In one embodiment, a processor comprises: at least one core formed on a die to execute instructions; a first memory controller to interface with an in-package memory; a second memory controller to interface with a platform memory to couple to the processor; and the in-package memory located within a package of the processor, where the in-package memory is to be identified as a more distant memory with respect to the at least one core than the platform memory. Other embodiments are described and claimed.

公开(公告)号：US10048736B2

公开(公告)日：2018-08-14

申请号：US14580150

申请日：2014-12-22

Applicant: Intel Corporation

Inventor： Jonathan M. Eastep ,  Richard J. Greco

IPC: G06F9/46 ,  G06F1/32 ,  G06F9/48 ,  G06F9/50 ,  G06F1/18

Abstract: Methods and apparatus to provide holistic global performance and power management are described. In an embodiment, logic (e.g., coupled to each compute node of a plurality of compute nodes) causes determination of a policy for power and performance management across the plurality of compute nodes. The policy is coordinated across the plurality of compute nodes to manage a job to one or more objective functions, where the job includes a plurality of tasks that are to run concurrently on the plurality of compute nodes. Other embodiments are also disclosed and claimed.

公开(公告)号：US12093104B1

公开(公告)日：2024-09-17

申请号：US18222937

申请日：2023-07-17

Applicant: Intel Corporation

Inventor： Jonathan M. Eastep ,  Richard J. Greco

IPC: G06F1/3203 ,  G06F1/3234 ,  G06F1/324 ,  G06F1/329 ,  G06F9/48 ,  G06F9/50 ,  G06N20/00

CPC classification number: G06F1/3203 ,  G06F1/324 ,  G06F1/3265 ,  G06F1/329 ,  G06F9/4893 ,  G06F9/5094 ,  G06N20/00

Abstract: Methods and apparatus to provide holistic global performance and power management are described. In an embodiment, logic (e.g., coupled to each compute node of a plurality of compute nodes) causes determination of a policy for power and performance management across the plurality of compute nodes. The policy is coordinated across the plurality of compute nodes to manage a job to one or more objective functions, where the job includes a plurality of tasks that are to run concurrently on the plurality of compute nodes. Other embodiments are also disclosed and claimed.

公开(公告)号：US11650652B2

公开(公告)日：2023-05-16

申请号：US17357479

申请日：2021-06-24

Applicant: INTEL CORPORATION

Inventor： Federico Ardanaz ,  Jonathan M. Eastep ,  Richard J. Greco ,  Ramkumar Nagappan ,  Alan B. Kyker

IPC: G06F1/32 ,  G06F1/3234 ,  G06F1/3287 ,  G06F1/3293

CPC classification number: G06F1/325 ,  G06F1/3287 ,  G06F1/3293 ,  Y02D10/00

Abstract: Apparatus, systems, and methods provide an interface between a plurality of hardware resources of a node and a power manager. The interface is configured to define one or more resource groups to expose to the power manager for power measurement and control, assign the plurality of hardware resources to the one or more resource groups, and provide a power allowance to each resource group.

公开(公告)号：US11526440B2

公开(公告)日：2022-12-13

申请号：US16433671

申请日：2019-06-06

Applicant: Intel Corporation

Inventor： Avinash Sodani ,  Robert J. Kyanko ,  Richard J. Greco ,  Andreas Kleen ,  Milind B. Girkar ,  Christopher M. Cantalupo

IPC: G06F12/00 ,  G06F13/00 ,  G06F12/06 ,  G06F12/02

Abstract: In one embodiment, a processor comprises: at least one core formed on a die to execute instructions; a first memory controller to interface with an in-package memory; a second memory controller to interface with a platform memory to couple to the processor; and the in-package memory located within a package of the processor, where the in-package memory is to be identified as a more distant memory with respect to the at least one core than the platform memory. Other embodiments are described and claimed.