公开(公告)号：US11121173B2

公开(公告)日：2021-09-14

申请号：US16662732

申请日：2019-10-24

Applicant: International Business Machines Corporation

Inventor： Ashim Dutta ,  Michael Rizzolo

IPC: H01L27/22 ,  H01L21/263 ,  H01L43/10 ,  H01L43/12 ,  H01L23/538

Abstract: Techniques for preserving the underlying dielectric layer during MRAM device formation are provided. In one aspect, a method of forming an MRAM device includes: depositing a first dielectric cap layer onto a substrate over logic and memory areas of the substrate; depositing a sacrificial metal layer onto the first dielectric cap layer; patterning the sacrificial metal layer, wherein the patterned sacrificial metal layer is present over the first dielectric cap layer in at least the logic area; depositing a second dielectric cap layer onto the first dielectric cap layer; forming an MRAM stack on the second dielectric cap layer; patterning the MRAM stack using ion beam etching into at least one memory cell, wherein the patterned sacrificial metal layer protects the first dielectric cap layer in the logic area; and removing the patterned sacrificial metal layer. An MRAM device is also provided.

公开(公告)号：US20210126051A1

公开(公告)日：2021-04-29

申请号：US16662732

申请日：2019-10-24

Applicant: International Business Machines Corporation

Inventor： Ashim Dutta ,  Michael Rizzolo

IPC: H01L27/22 ,  H01L21/263 ,  H01L23/538 ,  H01L43/12 ,  H01L43/10

Abstract: Techniques for preserving the underlying dielectric layer during MRAM device formation are provided. In one aspect, a method of forming an MRAM device includes: depositing a first dielectric cap layer onto a substrate over logic and memory areas of the substrate; depositing a sacrificial metal layer onto the first dielectric cap layer; patterning the sacrificial metal layer, wherein the patterned sacrificial metal layer is present over the first dielectric cap layer in at least the logic area; depositing a second dielectric cap layer onto the first dielectric cap layer; forming an MRAM stack on the second dielectric cap layer; patterning the MRAM stack using ion beam etching into at least one memory cell, wherein the patterned sacrificial metal layer protects the first dielectric cap layer in the logic area; and removing the patterned sacrificial metal layer. An MRAM device is also provided.

公开(公告)号：US20210091306A1

公开(公告)日：2021-03-25

申请号：US16582762

申请日：2019-09-25

Applicant: International Business Machines Corporation

Inventor： Ashim Dutta ,  Chih-Chao Yang ,  Lijuan Zou ,  John Arnold

IPC: H01L43/12 ,  H01L27/22 ,  H01L43/02 ,  H01L43/10

Abstract: Controlled IBE techniques for MRAM stack patterning are provided. In one aspect, a method of forming an MRAM device includes: patterning an MRAM stack disposed on a dielectric into individual memory cells using IBE landing on the dielectric while dynamically adjusting an etch time to compensate for variations in a thickness of the MRAM stack, wherein each of the memory cells includes a bottom electrode, an MTJ, and a top electrode; removing foot flares from the bottom electrode of the memory cells which are created during the patterning of the MRAM stack; removing residue from sidewalls of the memory cells which includes metal redeposited during the patterning of the MRAM stack and during the removing of the foot flares; and covering the memory cells in a dielectric encapsulant. An MRAM device is also provided.

公开(公告)号：US10886462B2

公开(公告)日：2021-01-05

申请号：US16194443

申请日：2018-11-19

Applicant: International Business Machines Corporation

Inventor： Ashim Dutta ,  Ekmini Anuja de Silva ,  Jennifer Church ,  Luciana Meli Thompson

IPC: H01L43/12 ,  H01L43/02 ,  H01L27/22 ,  H01L21/02

Abstract: A method for selectively encapsulating embedded memory pillars in a semiconductor device includes coating a passivation layer on a first dielectric surface on a first outer dielectric layer present in the semiconductor device. The passivation layer adheres to the dielectric surface selective to metal. The method includes depositing an encapsulation layer on side and top surfaces of the embedded memory pillars. The passivation layer prevents deposition of the encapsulation layer on the first dielectric surface of the first outer layer dielectric. The method includes removing the first outer dielectric layer from horizontal subraces around the embedded memory pillar and the encapsulation layer from the top surface of the embedded memory pillars.

公开(公告)号：US10796911B2

公开(公告)日：2020-10-06

申请号：US16806183

申请日：2020-03-02

Applicant: International Business Machines Corporation

Inventor： Michael Rizzolo ,  Ashim Dutta ,  Oscar van der Straten ,  Chih-Chao Yang

IPC: H01L21/033 ,  H01L43/12 ,  H01L43/02

Abstract: A method for manufacturing a semiconductor device includes forming one or more memory device layers over a contact structure. In the method, a plurality of hardmask layers are deposited on the one or more memory device layers in a stacked configuration. Alternating hardmask layers of the stacked configuration are different from each other in at least one respect. The method further includes patterning the plurality of hardmask layers and the one or more memory device layers into a pillar over the contact structure.

公开(公告)号：US10672611B2

公开(公告)日：2020-06-02

申请号：US16165311

申请日：2018-10-19

Applicant: International Business Machines Corporation

Inventor： Michael Rizzolo ,  Ashim Dutta ,  Oscar van der Straten ,  Chih-Chao Yang

IPC: H01L21/033 ,  H01L43/12 ,  H01L43/02

Abstract: A method for manufacturing a semiconductor device includes forming one or more memory device layers over a contact structure. In the method, a plurality of hardmask layers are deposited on the one or more memory device layers in a stacked configuration. Alternating hardmask layers of the stacked configuration are different from each other in at least one respect. The method further includes patterning the plurality of hardmask layers and the one or more memory device layers into a pillar over the contact structure.

公开(公告)号：US10656527B2

公开(公告)日：2020-05-19

申请号：US15850192

申请日：2017-12-21

Applicant: International Business Machines Corporation

Inventor： Ekmini Anuja De Silva ,  Indira Seshadri ,  Jing Guo ,  Ashim Dutta ,  Nelson Felix

IPC: G03F7/40 ,  G03F7/20 ,  H01L21/308 ,  H01L21/027 ,  G03F1/22 ,  H01L21/033 ,  G03F1/54

Abstract: A lithographic patterning method includes forming a multi-layer patterning material film stack on a semiconductor substrate. Forming the patterning material film stack more particularly includes forming a hard mask layer and forming a resist layer over the hard mask layer. The hard mask layer is configured to support selective deposition of a metal-containing layer on the resist layer, the selective deposition of the metal-containing layer on the resist layer occurring after pattern development. The method further includes exposing the multi-layer patterning material film stack to patterning radiation to form a desired pattern in the resist layer, developing the pattern formed in the resist layer, and selectively depositing the metal-containing layer on the developed pattern in the resist layer. The selective deposition avoids deposition of the metal-containing layer on portions of the hard mask layer corresponding to respective openings in the resist layer.

公开(公告)号：US20200152514A1

公开(公告)日：2020-05-14

申请号：US16183787

申请日：2018-11-08

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Ashim Dutta ,  Jennifer Church ,  Ekmini A. de Silva ,  Luciana M. Thompson

IPC: H01L21/768 ,  H01L21/311 ,  H01L21/321 ,  H01L29/66 ,  H01L29/78

Abstract: A method for forming one or more self-aligned contacts on a semiconductor device includes applying a protective layer on an oxide surface above a source and drain of the semiconductor device. The protective layer covers a top surface of the oxide surface selective to nitride above a gate contact pillar. A sacrificial layer is applied to the nitride surface. The sacrificial layer is deposited only on the nitride surface that is selective to the oxide layer coated with the protective layer. The protective layer is removed from the oxide surface and source/drain contact holes are etched in the oxide surface to form self-aligned contacts on the semiconductor device.

公开(公告)号：US20250125192A1

公开(公告)日：2025-04-17

申请号：US18380478

申请日：2023-10-16

Applicant: International Business Machines Corporation

Inventor： Ashim Dutta ,  Katherine Luedders ,  Chih-Chao Yang

IPC: H01L21/768 ,  H01L23/528 ,  H01L23/532

Abstract: A back-end-of-the-line (BEOL) interconnect structure is provided that includes a top via structure located on a metal line. An air gap is located adjacent to, and around, the metal line and top via structure. This air gap includes a lower portion adjacent to the metal line and an upper portion adjacent to the top via structure. Such an air gap can extend BEOL interconnect scaling for 2 nm technology node and below. Methods of forming such an BEOL interconnect structure are also provided.

公开(公告)号：US20250089347A1

公开(公告)日：2025-03-13

申请号：US18465376

申请日：2023-09-12

Applicant: International Business Machines Corporation

Inventor： Ashim Dutta ,  Brandon Noland Canedy ,  Chih-Chao Yang ,  Shravana Kumar Katakam

IPC: H01L27/08 ,  H01L21/02 ,  H01L21/311 ,  H01L21/3205 ,  H01L21/3213

Abstract: A structure that includes a plurality of circular metal elements that are concentrically arranged and connected through a plurality of metal connectors, wherein the structure forms a circular resistor.