公开(公告)号：US20240304546A1

公开(公告)日：2024-09-12

申请号：US18179417

申请日：2023-03-07

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Oscar van der Straten ,  Koichi Motoyama ,  Chih-Chao Yang

IPC: H01L23/528 ,  H01L21/768

CPC classification number: H01L23/5283 ,  H01L21/76804 ,  H01L21/76849 ,  H01L21/76883 ,  H01L23/53238 ,  H01L23/53266

Abstract: A structure including a homogeneous interconnect structure embedded in a dielectric layer, where the homogeneous interconnect structure includes a first region and a second region one above another, where the first region comprises a width which increases relative to height, and where the second region comprises a width which decreases relative to height.

公开(公告)号：US20240153868A1

公开(公告)日：2024-05-09

申请号：US18053772

申请日：2022-11-09

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Koichi Motoyama ,  Oscar van der Straten ,  Ruilong Xie ,  Chih-Chao Yang

IPC: H01L23/522 ,  H01L21/768 ,  H01L23/532

CPC classification number: H01L23/5226 ,  H01L21/76807 ,  H01L21/76843 ,  H01L21/76877 ,  H01L23/53238 ,  H01L23/53266

Abstract: Embodiments of present invention provide an interconnect structure. The interconnect structure includes a first metal line in a first inter-level dielectric (ILD) layer; one or more second metal lines in a second ILD layer above the first metal line and above the first ILD layer; a third metal line in a third ILD layer above the one or more second metal lines and above the second ILD layer; and a skipvia connecting the third metal line with the first metal line, wherein the first, the one or more second, and the third metal lines are made of a first conductive material and the skipvia is made of a second conductive material, and the first conductive material is different from the second conductive material. A method of forming the above interconnect structure is also provided.

公开(公告)号：US20240032435A1

公开(公告)日：2024-01-25

申请号：US17814243

申请日：2022-07-22

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Koichi Motoyama ,  Oscar van der Straten ,  Chih-Chao Yang

IPC: H01L43/08 ,  H01L27/22 ,  H01L43/02 ,  H01L43/12 ,  G11C11/16

CPC classification number: H01L43/08 ,  H01L27/222 ,  H01L43/02 ,  H01L43/12 ,  G11C11/161

Abstract: Embodiments of present invention provide a method of forming a MRAM structure. The method includes patterning a bottom electrode layer and a first ferromagnetic layer on top of the bottom electrode layer; depositing a dielectric layer, the dielectric layer covering the bottom electrode layer and the first ferromagnetic layer; creating an opening in the dielectric layer, the opening exposing a portion of the first ferromagnetic layer; forming a tunnel barrier layer inside the opening; forming a second ferromagnetic layer on top of the tunnel barrier layer; patterning the tunnel barrier layer and the second ferromagnetic layer; and forming a top electrode layer on top of the second ferromagnetic layer. Structures formed thereby are also provided.

公开(公告)号：US20230402079A1

公开(公告)日：2023-12-14

申请号：US17806790

申请日：2022-06-14

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Oscar van der Straten ,  Koichi Motoyama ,  Chih-Chao Yang

IPC: G11C11/16 ,  H01L43/08 ,  H01L43/02 ,  H01L43/12 ,  H01L27/22

CPC classification number: G11C11/161 ,  H01L43/08 ,  H01L43/02 ,  H01L43/12 ,  H01L27/222

Abstract: Embodiments of the invention include a semiconductor structure with a first magneto-resistive random access memory (MRAM) pillar with a bottom electrode layer, a reference layer connected above the bottom electrode layer, a free layer, and a tunnel barrier between the reference layer and the free layer. The MRAM pillar includes a pillar diameter. The semiconductor structure also includes a coaxial top electrode with a top diameter that is less than the pillar diameter.

公开(公告)号：US20230186962A1

公开(公告)日：2023-06-15

申请号：US17644349

申请日：2021-12-15

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Ashim Dutta ,  Dominik Metzler ,  Oscar van der Straten ,  Theodorus E. Standaert

IPC: G11C11/16 ,  H01L27/22 ,  H01L43/10 ,  H01L43/08 ,  H01L43/02 ,  H01L43/12 ,  H01L23/522 ,  H01L21/768

CPC classification number: G11C11/161 ,  H01L27/222 ,  H01L43/10 ,  H01L43/08 ,  H01L43/02 ,  H01L43/12 ,  H01L23/5226 ,  H01L21/76816

Abstract: A memory device with modified top electrode contact includes a memory pillar composed of a bottom electrode, a magnetic random-access memory (MRAM) stack above the bottom electrode, and a top electrode above the MRAM stack. A first portion of an encapsulation layer is disposed along opposite sidewalls of the bottom electrode, on opposite sidewalls of the MRAM stack and on opposite sidewalls of a bottom portion of the top electrode, a second portion of the encapsulation layer is located above a second dielectric layer. A metal cap is located above an uppermost surface and opposite sidewalls of a top portion of the top electrode and above an uppermost surface of the first portion of the encapsulation layer. A second conductive interconnect is formed above a top surface of the metal cap wrapping around opposite sidewalls of the first portion of the encapsulation layer and opposite sidewalls of the metal cap.

公开(公告)号：US20230144157A1

公开(公告)日：2023-05-11

申请号：US17520672

申请日：2021-11-07

Applicant: International Business Machines Corporation

Inventor： Koichi Motoyama ,  Oscar van der Straten ,  Joseph F. Maniscalco ,  Chih-Chao Yang

IPC: H01L43/12 ,  H01L27/22 ,  H01L43/02

CPC classification number: H01L43/12 ,  H01L27/222 ,  H01L43/02

Abstract: Embodiments of the invention include a method for fabricating a semiconductor device and the resulting structure. A first set of spacers are formed on the sidewalls of a bottom electrode. A reference layer is formed on the spacers and the bottom electrode. A second set of spacers are formed on the sidewalls of the first set of spacers and the reference layer. A tunnel barrier is formed on the reference layer and the second set of spacers. A free layer is formed on the tunnel barrier, where a width of the free layer is greater than a width of the reference layer. A metal hardmask is formed on the free layer. A third set of spacers are formed on the sidewalls of the metal hardmask, the free layer, the tunnel barrier, and the second set of spacers.

公开(公告)号：US20230046923A1

公开(公告)日：2023-02-16

申请号：US17401415

申请日：2021-08-13

Applicant: International Business Machines Corporation

Inventor： Eric Raymond Evarts ,  Virat Vasav Mehta ,  Oscar van der Straten

IPC: H01L27/22 ,  H01L43/06 ,  H01L43/04 ,  G11C11/16 ,  H01L43/14

Abstract: A spin-orbit torque magnetoresistive random-access memory device formed by fabricating a spin-Hall-effect (SHE) layer above and in electrical contact with a transistor, forming a spin-orbit-torque (SOT) magnetoresistive random access memory (MRAM) cell stack disposed above and in electrical contact with the SHE rail, wherein the SOT-MRAM cell stack comprises a free layer, a tunnel junction layer, a reference layer, and a diode structure, forming a write line disposed in electrical contact with the SHE rail, forming a protective dielectric layer covering a portion of the SOT-MRAM cell stack, and forming a read line disposed above and adjacent to the diode structure.

公开(公告)号：US20220416161A1

公开(公告)日：2022-12-29

申请号：US17358223

申请日：2021-06-25

Applicant: International Business Machines Corporation

Inventor： Kangguo Cheng ,  Carl Radens ,  JUNTAO LI ,  Ruilong Xie ,  Praneet Adusumilli ,  Oscar van der Straten ,  Alexander Reznicek

IPC: H01L45/00

Abstract: A ring-shaped heater, system, and method to gradually change the conductance of the phase change memory through a concentric ring-shaped heater. The system may include a phase change memory. The phase change memory may include a bottom electrode. The phase change memory may also include a ring-shaped heater patterned on top of the bottom electrode, the ring-shaped heater including: a plurality of concentric conductive heating layers, and a plurality of insulator spacers, where each insulator spacer separates each conductive heating layer. The phase change memory may also include a phase change material proximately connected to the ring-shaped heater. The phase change memory may also include a top electrode proximately connected to the phase change material.

公开(公告)号：US11158538B2

公开(公告)日：2021-10-26

申请号：US16781038

申请日：2020-02-04

Applicant: International Business Machines Corporation

Inventor： Joseph F. Maniscalco ,  Koichi Motoyama ,  Oscar van der Straten ,  Scott A. DeVries ,  Alexander Reznicek

IPC: H01L21/768 ,  H01L23/532

Abstract: An interconnect structure, and a method for forming the same includes forming recess within a dielectric layer and conformally depositing a barrier layer within the recess. A cobalt-infused ruthenium liner is formed above the barrier layer, the cobalt containing ruthenium liner formed by stacking a second liner above a first liner, the first liner positioned above the barrier layer. The first liner includes ruthenium while the second liner includes cobalt. Cobalt atoms migrate from the second liner to the first liner forming the cobalt-infused ruthenium liner. A conductive material is deposited above the cobalt-infused ruthenium liner to fill the recess followed by a capping layer made of cobalt.

公开(公告)号：US20210327803A1

公开(公告)日：2021-10-21

申请号：US16849342

申请日：2020-04-15

Applicant: International Business Machines Corporation

Inventor： Koichi Motoyama ,  Oscar van der Straten ,  Kenneth Chun Kuen Cheng ,  Joseph F. Maniscalco

IPC: H01L23/522 ,  H01L23/528 ,  H01L23/532 ,  H01L21/768

Abstract: An interconnect structure of an integrated circuit (IC) in which dielectric material defines upper and lower cavities and a via cavity communicative with the upper and lower cavities at upper and lower ends thereof. The interconnect structure includes first conductive material filling the upper and lower cavities to form upper and lower lines, respectively and second conductive material filling the via cavity from the upper end thereof to the lower end thereof to form a via electrically communicative with the upper and lower lines.