公开(公告)号：US11515427B2

公开(公告)日：2022-11-29

申请号：US16901852

申请日：2020-06-15

Applicant: International Business Machines Corporation

Inventor： Kai Zhao ,  Shahab Siddiqui ,  Daniel James Dechene ,  Rishikesh Krishnan ,  Charlotte DeWan Adams

IPC: H01L29/78 ,  H01L29/786 ,  H01L29/423 ,  H01L29/66 ,  H01L21/8234 ,  H01L29/08

Abstract: Epitaxially grow first lower source-drain regions within a substrate. Portions of the substrate adjacent the lower regions are doped to form second lower source-drain regions. An undoped silicon layer is formed over the first and second lower regions. Etch completely through the undoped layer into the first and second lower regions to form fins and to define bottom junctions beneath the fins. The fins and bottom junctions define intermediate cavities. Form lower spacers, gates, and upper spacers in the cavities; form top junctions on outer surfaces of the fins; and form epitaxially grown first upper source-drain regions outward of the upper spacers and opposite the first lower regions. The first upper regions are doped the same as the first lower regions. Form second upper source-drain regions outward of the upper spacers and opposite the second lower regions; these are doped the same as the second lower regions.

公开(公告)号：US20220069104A1

公开(公告)日：2022-03-03

申请号：US17521964

申请日：2021-11-09

Applicant: International Business Machines Corporation

Inventor： Shahab Siddiqui ,  Koji Watanabe ,  Charlotte DeWan Adams ,  Kai Zhao ,  Daniel James Dechene ,  Rishikesh Krishnan

IPC: H01L29/66 ,  H01L29/417 ,  H01L21/8234 ,  H01L29/786 ,  H01L21/02 ,  H01L29/423

Abstract: A method of forming a semiconductor structure includes forming a first nanosheet stack and a second nanosheet stack on a semiconductor substrate. The first nanosheet stack includes a plurality of alternating first sacrificial layers and first channel layers. The first sacrificial layers each define a first sacrificial height. The second nanosheet stack includes a plurality of alternating second sacrificial layers and second channel layers. The second sacrificial layers each define a second sacrificial height greater than the first sacrificial height of the first sacrificial layers. The method further includes removing the first and second sacrificial layers respectively from the first and second nanosheet stacks. A metal gate is deposited over the first and second nanosheet stacks to form respective first and second nanosheet transistor structures.

公开(公告)号：US20190259754A1

公开(公告)日：2019-08-22

申请号：US16401141

申请日：2019-05-02

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Ruqiang Bao ,  Unoh Kwon ,  Kai Zhao

IPC: H01L27/092 ,  H01L21/8238 ,  H01L29/423 ,  H01L29/49

Abstract: A semiconductor device includes a first transistor formed on a substrate, the first transistor including a channel region positioned on the substrate; a second transistor formed on the substrate, the second transistor including a channel region positioned on the substrate; a high-k dielectric layer disposed on the channel region of the first transistor and the channel region of the second transistor; a first transistor metal gate positioned in contact with the high-k dielectric on the first transistor; a second transistor metal gate positioned in contact with the high-k dielectric on the second transistor; an oxygen absorbing barrier disposed in contact with the high-k dielectric between the first transistor and the second transistor; and a conductive electrode material disposed on the first transistor, the second transistor, and the oxygen absorbing barrier.

公开(公告)号：US20170200719A1

公开(公告)日：2017-07-13

申请号：US14994650

申请日：2016-01-13

Applicant: International Business Machines Corporation

Inventor： Ruqiang Bao ,  Unoh Kwon ,  Kai Zhao

IPC: H01L27/092 ,  H01L29/66 ,  H01L21/8238 ,  H01L29/51 ,  H01L29/49 ,  H01L29/423

CPC classification number: H01L27/092 ,  H01L21/823807 ,  H01L21/823828 ,  H01L21/823842 ,  H01L29/42372 ,  H01L29/4958 ,  H01L29/4966 ,  H01L29/517

Abstract: A semiconductor device includes a first transistor formed on a substrate, the first transistor including a channel region positioned on the substrate; a second transistor formed on the substrate, the second transistor including a channel region positioned on the substrate; a high-k dielectric layer disposed on the channel region of the first transistor and the channel region of the second transistor; a first transistor metal gate positioned in contact with the high-k dielectric on the first transistor; a second transistor metal gate positioned in contact with the high-k dielectric on the second transistor; an oxygen absorbing barrier disposed in contact with the high-k dielectric between the first transistor and the second transistor; and a conductive electrode material disposed on the first transistor, the second transistor, and the oxygen absorbing barrier.

公开(公告)号：US20150084132A1

公开(公告)日：2015-03-26

申请号：US14037423

申请日：2013-09-26

Applicant: International Business Machines Corporation

Inventor： Anthony I-Chih Chou ,  Arvind Kumar ,  Shreesh Narasimha ,  Claude Ortolland ,  Kai Zhao

IPC: H01L29/51 ,  H01L21/8238 ,  H01L27/092

CPC classification number: H01L29/518 ,  H01L21/28176 ,  H01L21/823821 ,  H01L21/823842 ,  H01L27/0924 ,  H01L29/511 ,  H01L29/513 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/78

Abstract: Standard High-K metal gate (HKMG) CMOS technologies fabricated using the replacement metal gate (RMG), also known as gate-last, integration flow, are susceptible to oxygen ingress into the high-K gate dielectric layer and oxygen diffusion into the gate dielectric and semiconductor channel region. The oxygen at the gate dielectric and semiconductor channel interface induces unwanted oxide regrowth that results in an effective oxide thickness increase, and transistor threshold voltage shifts, both of which are highly variable and degrade semiconductor chip performance. By introducing silicon nitride deposited at low temperature, after the metal gate formation, the oxygen ingress and gate dielectric regrowth can be avoided, and a high semiconductor chip performance is maintained.

Abstract translation: 使用替代金属栅极（RMG）制造的标准高K金属栅极（HKMG）CMOS技术也被称为最终集成流，易受氧进入高K栅介质层和氧气扩散入栅极 电介质和半导体沟道区。 栅极电介质和半导体沟道界面处的氧会引起不必要的氧化物再生长，导致有效的氧化物厚度增加，并且晶体管阈值电压偏移，这两者都是高度可变的并且降低半导体芯片性能。 通过引入在低温下沉积的氮化硅，在金属栅极形成之后，可以避免氧进入和栅介质再生长，并且保持高的半导体芯片性能。