公开(公告)号：US10354999B2

公开(公告)日：2019-07-16

申请号：US15723283

申请日：2017-10-03

Applicant: International Business Machines Corporation

Inventor： Ruqiang Bao ,  Unoh Kwon ,  Kai Zhao

IPC: H01L29/49 ,  H01L29/51 ,  H01L27/092 ,  H01L29/423 ,  H01L21/8238

Abstract: A semiconductor device includes a first transistor formed on a substrate, the first transistor including a channel region positioned on the substrate; a second transistor formed on the substrate, the second transistor including a channel region positioned on the substrate; a high-k dielectric layer disposed on the channel region of the first transistor and the channel region of the second transistor; a first transistor metal gate positioned in contact with the high-k dielectric on the first transistor; a second transistor metal gate positioned in contact with the high-k dielectric on the second transistor; an oxygen absorbing barrier disposed in contact with the high-k dielectric between the first transistor and the second transistor; and a conductive electrode material disposed on the first transistor, the second transistor, and the oxygen absorbing barrier.

公开(公告)号：US11888048B2

公开(公告)日：2024-01-30

申请号：US17521964

申请日：2021-11-09

Applicant: International Business Machines Corporation

Inventor： Shahab Siddiqui ,  Koji Watanabe ,  Charlotte DeWan Adams ,  Kai Zhao ,  Daniel James Dechene ,  Rishikesh Krishnan

IPC: H01L29/66 ,  H01L29/417 ,  H01L21/8234 ,  H01L29/786 ,  H01L21/02 ,  H01L29/423

CPC classification number: H01L29/6675 ,  H01L21/0259 ,  H01L21/823431 ,  H01L29/41733 ,  H01L29/42384 ,  H01L29/7869

Abstract: A method of forming a semiconductor structure includes forming a first nanosheet stack and a second nanosheet stack on a semiconductor substrate. The first nanosheet stack includes a plurality of alternating first sacrificial layers and first channel layers. The first sacrificial layers each define a first sacrificial height. The second nanosheet stack includes a plurality of alternating second sacrificial layers and second channel layers. The second sacrificial layers each define a second sacrificial height greater than the first sacrificial height of the first sacrificial layers. The method further includes removing the first and second sacrificial layers respectively from the first and second nanosheet stacks. A metal gate is deposited over the first and second nanosheet stacks to form respective first and second nanosheet transistor structures.

公开(公告)号：US20220190125A1

公开(公告)日：2022-06-16

申请号：US17118853

申请日：2020-12-11

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Heng Wu ,  Ruilong Xie ,  Tian Shen ,  Kai Zhao

IPC: H01L29/417 ,  H01L29/78 ,  H01L29/45 ,  H01L27/092 ,  H01L21/8238

Abstract: An embodiment of the invention may include a Vertical Field Effect Transistor (VFET) structure, and method of making that structure, having a first VFET and a second VFET. The first VFET may include a single liner between a first source/drain epi and a contact. The second VFET may include two liners between a second source/drain epi and a contact. This may enable proper contact liner matching for differing VFET devices.

公开(公告)号：US11211474B2

公开(公告)日：2021-12-28

申请号：US16742295

申请日：2020-01-14

Applicant: International Business Machines Corporation

Inventor： Shahab Siddiqui ,  Koji Watanabe ,  Charlotte DeWan Adams ,  Kai Zhao ,  Daniel James Dechene ,  Rishikesh Krishnan

IPC: H01L29/66 ,  H01L29/417 ,  H01L21/8234 ,  H01L29/786 ,  H01L21/02 ,  H01L29/423

Abstract: A method of forming a semiconductor structure includes forming a first nanosheet stack and a second nanosheet stack on a semiconductor substrate. The first nanosheet stack includes a plurality of alternating first sacrificial layers and first channel layers. The first sacrificial layers each define a first sacrificial height. The second nanosheet stack includes a plurality of alternating second sacrificial layers and second channel layers. The second sacrificial layers each define a second sacrificial height greater than the first sacrificial height of the first sacrificial layers. The method further includes removing the first and second sacrificial layers respectively from the first and second nanosheet stacks. A metal gate is deposited over the first and second nanosheet stacks to form respective first and second nanosheet transistor structures.

公开(公告)号：US20160005620A1

公开(公告)日：2016-01-07

申请号：US14323036

申请日：2014-07-03

Applicant: International Business Machines Corporation

Inventor： Takashi Ando ,  Claude Ortolland ,  Kai Zhao

IPC: H01L21/3115 ,  H01L29/51 ,  H01L29/66

CPC classification number: H01L21/3115 ,  H01L21/02323 ,  H01L21/02337 ,  H01L21/28176 ,  H01L21/28194 ,  H01L29/4966 ,  H01L29/511 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/6656

Abstract: A method of manufacturing a semiconductor structure, by depositing a dielectric layer is a dummy gate, or an existing gate structure, prior to the formation of gate spacers. Following the formation of spacers, and in some embodiments replacing a dummy gate with a final gate structure, oxygen is introduced to a gate dielectric through a diffusion process, using the deposited dielectric layer as a diffusion pathway.

Abstract translation: 在形成栅极间隔物之前，通过沉积介电层制造半导体结构的方法是虚拟栅极或现有栅极结构。 在形成间隔物之后，并且在一些实施例中用最终栅极结构代替虚拟栅极，通过使用沉积的介电层作为扩散路径，通过扩散工艺将氧引入栅极电介质。

公开(公告)号：US12068415B2

公开(公告)日：2024-08-20

申请号：US17966817

申请日：2022-10-15

Applicant: International Business Machines Corporation

Inventor： Kai Zhao ,  Shahab Siddiqui ,  Daniel James Dechene ,  Rishikesh Krishnan ,  Charlotte DeWan Adams

IPC: H01L29/78 ,  H01L21/8234 ,  H01L29/08 ,  H01L29/423 ,  H01L29/66 ,  H01L29/786

CPC classification number: H01L29/78642 ,  H01L21/823418 ,  H01L29/0847 ,  H01L29/42392 ,  H01L29/66666 ,  H01L29/66795 ,  H01L29/785

Abstract: Epitaxially grow first lower source-drain regions within a substrate. Portions of the substrate adjacent the lower regions are doped to form second lower source-drain regions. An undoped silicon layer is formed over the first and second lower regions. Etch completely through the undoped layer into the first and second lower regions to form fins and to define bottom junctions beneath the fins. The fins and bottom junctions define intermediate cavities. Form lower spacers, gates, and upper spacers in the cavities; form top junctions on outer surfaces of the fins; and form epitaxially grown first upper source-drain regions outward of the upper spacers and opposite the first lower regions. The first upper regions are doped the same as the first lower regions. Form second upper source-drain regions outward of the upper spacers and opposite the second lower regions; these are doped the same as the second lower regions.

公开(公告)号：US11908907B2

公开(公告)日：2024-02-20

申请号：US17118853

申请日：2020-12-11

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Heng Wu ,  Ruilong Xie ,  Tian Shen ,  Kai Zhao

IPC: H01L29/417 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/78 ,  H01L29/45 ,  H01L29/66

CPC classification number: H01L29/41741 ,  H01L21/823814 ,  H01L21/823871 ,  H01L21/823885 ,  H01L27/092 ,  H01L29/45 ,  H01L29/66666 ,  H01L29/7827

Abstract: An embodiment of the invention may include a Vertical Field Effect Transistor (VFET) structure, and method of making that structure, having a first VFET and a second VFET. The first VFET may include a single liner between a first source/drain epi and a contact. The second VFET may include two liners between a second source/drain epi and a contact. This may enable proper contact liner matching for differing VFET devices.

公开(公告)号：US20230207553A1

公开(公告)日：2023-06-29

申请号：US17562331

申请日：2021-12-27

Applicant: International Business Machines Corporation

Inventor： Ruilong Xie ,  Kisik Choi ,  Somnath Ghosh ,  Sagarika Mukesh ,  Albert Chu ,  Albert M. Young ,  Balasubramanian S. Pranatharthiharan ,  Huiming Bu ,  Kai Zhao ,  John Christopher Arnold ,  Brent A. Anderson ,  Dechao Guo

IPC: H01L27/02 ,  H01L29/423 ,  H01L29/06 ,  H01L27/092 ,  H01L27/12 ,  H01L21/8234 ,  H01L21/762

CPC classification number: H01L27/0207 ,  H01L29/42392 ,  H01L29/0673 ,  H01L27/092 ,  H01L27/1251 ,  H01L21/823475 ,  H01L21/76229

Abstract: A device comprises a first interconnect structure, a second interconnect structure, a first cell comprising a first transistor, a second cell comprising a second transistor, a first contact connecting a source/drain element of the first transistor to the first interconnect structure, and second contact connecting a source/drain element of the second transistor to the second interconnect structure. The first cell is disposed adjacent to the second cell with the first transistor disposed adjacent to the second transistor. The first and second cells are disposed between the first and second interconnect structures.

公开(公告)号：US20230029561A1

公开(公告)日：2023-02-02

申请号：US17966817

申请日：2022-10-15

Applicant: International Business Machines Corporation

Inventor： Kai Zhao ,  Shahab Siddiqui ,  Daniel James Dechene ,  Rishikesh Krishnan ,  Charlotte DeWan Adams

IPC: H01L29/786 ,  H01L29/66 ,  H01L21/8234 ,  H01L29/423 ,  H01L29/08 ,  H01L29/78

Abstract: Epitaxially grow first lower source-drain regions within a substrate. Portions of the substrate adjacent the lower regions are doped to form second lower source-drain regions. An undoped silicon layer is formed over the first and second lower regions. Etch completely through the undoped layer into the first and second lower regions to form fins and to define bottom junctions beneath the fins. The fins and bottom junctions define intermediate cavities. Form lower spacers, gates, and upper spacers in the cavities; form top junctions on outer surfaces of the fins; and form epitaxially grown first upper source-drain regions outward of the upper spacers and opposite the first lower regions. The first upper regions are doped the same as the first lower regions. Form second upper source-drain regions outward of the upper spacers and opposite the second lower regions; these are doped the same as the second lower regions.

公开(公告)号：US20210391473A1

公开(公告)日：2021-12-16

申请号：US16901852

申请日：2020-06-15

Applicant: International Business Machines Corporation

Inventor： Kai Zhao ,  Shahab Siddiqui ,  Daniel James Dechene ,  Rishikesh Krishnan ,  Charlotte DeWan Adams

IPC: H01L29/786 ,  H01L29/423 ,  H01L29/66 ,  H01L29/08 ,  H01L29/78 ,  H01L21/8234

Abstract: Epitaxially grow first lower source-drain regions within a substrate. Portions of the substrate adjacent the lower regions are doped to form second lower source-drain regions. An undoped silicon layer is formed over the first and second lower regions. Etch completely through the undoped layer into the first and second lower regions to form fins and to define bottom junctions beneath the fins. The fins and bottom junctions define intermediate cavities. Form lower spacers, gates, and upper spacers in the cavities; form top junctions on outer surfaces of the fins; and form epitaxially grown first upper source-drain regions outward of the upper spacers and opposite the first lower regions. The first upper regions are doped the same as the first lower regions. Form second upper source-drain regions outward of the upper spacers and opposite the second lower regions; these are doped the same as the second lower regions.