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    STRUCTURE AND PROCESS TO DECOUPLE DEEP TRENCH CAPACITORS AND WELL ISOLATION
    5.
    发明申请
    STRUCTURE AND PROCESS TO DECOUPLE DEEP TRENCH CAPACITORS AND WELL ISOLATION 审中-公开
    结构和工艺分解深层电容电容器和隔离层

    公开(公告)号：US20150214244A1

    公开(公告)日：2015-07-30

    申请号：US14166155

    申请日：2014-01-28

    申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

    发明人： Herbert L. Ho ,  Sivananda K. Kanakasabapathy ,  Rishikesh Krishnan ,  Kern Rim

    IPC分类号： H01L27/12 ,  H01L27/08 ,  H01L21/324 ,  H01L21/306 ,  H01L21/762 ,  H01L49/02 ,  H01L27/02

    CPC分类号： H01L27/1203 ,  H01L21/3065 ,  H01L21/76224 ,  H01L21/84 ,  H01L27/0629 ,  H01L28/90

    摘要： Formation of deep trench capacitors and isolation structures are decoupled by completing the isolation structures prior to etching trenches for capacitors and forming capacitors therein or vice-versa. Such decoupling of the formation of these respective structures allows different materials to be used in the deep trench capacitors and the isolation structures such as use of low permeability or dielectric constant materials and/or low Young's modulus materials in isolation structures to provide reduced AC capacitive coupling across isolation structures and/or relief of stresses associated with use of high dielectric constant materials or metal-insulator-metal (MIM) structures in deep trench capacitors. Such decoupling also allows increased efficiency of use of reaction chambers for the deep trench capacitors and the isolation structures.

    摘要翻译： 深沟槽电容器和隔离结构的形成通过在蚀刻用于电容器的沟槽和在其中形成电容器之前完成隔离结构来解耦，反之亦然。 这些相应结构的形成的这种解耦允许在深沟槽电容器和隔离结构中使用不同的材料，例如在隔离结构中使用低导磁率或介电常数材料和/或低杨氏模量材料来提供减小的AC电容耦合 跨越隔离结构和/或释放与在深沟槽电容器中使用高介电常数材料或金属 - 绝缘体 - 金属（MIM）结构有关的应力。 这种去耦还允许增加用于深沟槽电容器和隔离结构的反应室的使用效率。

    Replacement gate with reduced gate leakage current
    6.
    发明授权
    Replacement gate with reduced gate leakage current 有权
    栅极泄漏电流降低的替代栅极

    公开(公告)号：US08809176B2

    公开(公告)日：2014-08-19

    申请号：US13842217

    申请日：2013-03-15

    申请人： International Business Machines Corporation

    发明人： Takashi Ando ,  Michael P. Chudzik ,  Rishikesh Krishnan ,  Siddarth A. Krishnan ,  Unoh Kwon ,  Keith Kwong Hon Wong

    IPC分类号： H01L21/3205

    CPC分类号： H01L21/28008 ,  H01L21/28088 ,  H01L21/823842 ,  H01L29/4966 ,  H01L29/66545 ,  H01L29/66606 ,  H01L29/7833 ,  H01L29/7843

    摘要： Replacement gate work function material stacks are provided, which provides a work function about the energy level of the conduction band of silicon. After removal of a disposable gate stack, a gate dielectric layer is formed in a gate cavity. A metallic compound layer including a metal and a non-metal element is deposited directly on the gate dielectric layer. At least one barrier layer and a conductive material layer is deposited and planarized to fill the gate cavity. The metallic compound layer includes a material having a work function about 4.4 eV or less, and can include a material selected from tantalum carbide and a hafnium-silicon alloy. Thus, the metallic compound layer can provide a work function that enhances the performance of an n-type field effect transistor employing a silicon channel.

    摘要翻译： 提供了替代栅极工作功能材料堆叠，其提供关于硅导带的能级的功函数。 在去除一次性栅极堆叠之后，在栅极腔中形成栅极电介质层。 包括金属和非金属元素的金属化合物层直接沉积在栅极介电层上。 沉积至少一个势垒层和导电材料层并平坦化以填充栅极腔。 金属化合物层包括功函数约4.4eV或更低的材料，并且可以包括选自碳化钽和铪硅合金的材料。 因此，金属化合物层可以提供增强采用硅通道的n型场效应晶体管的性能的功函数。

    NON-VOLATILE MEMORY STRUCTURE EMPLOYING HIGH-K GATE DIELECTRIC AND METAL GATE
    7.
    发明申请
    NON-VOLATILE MEMORY STRUCTURE EMPLOYING HIGH-K GATE DIELECTRIC AND METAL GATE 有权
    使用高K门电介质和金属门的非易失性存储器结构

    公开(公告)号：US20140057426A1

    公开(公告)日：2014-02-27

    申请号：US14066119

    申请日：2013-10-29

    申请人： International Business Machines Corporation

    发明人： Nicolas Breil ,  Michael P. Chudzik ,  Rishikesh Krishnan ,  Siddarth A. Krishnan ,  Unoh Kwon

    IPC分类号： H01L21/28 ,  H01L21/02

    CPC分类号： H01L21/28273 ,  H01L21/0228 ,  H01L21/823842 ,  H01L21/823857 ,  H01L21/823892 ,  H01L27/11546 ,  H01L29/42376 ,  H01L29/4958 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/7881

    摘要： A high dielectric constant (high-k) gate dielectric for a field effect transistor (FET) and a high-k tunnel dielectric for a non-volatile random access memory (NVRAM) device are simultaneously formed on a semiconductor substrate. A stack of at least one conductive material layer, a control gate dielectric layer, and a disposable material layer is subsequently deposited and lithographically patterned. A planarization dielectric layer is deposited and patterned, and disposable material portions are removed. A remaining portion of the control gate dielectric layer is preserved in the NVRAM device region, but is removed in the FET region. A conductive material is deposited in gate cavities to provide a control gate for the NVRAM device and a gate portion for the FET. Alternately, the control gate dielectric layer may replaced with a high-k control gate dielectric in the NVRAM device region.

    摘要翻译： 在半导体衬底上同时形成用于场效应晶体管（FET）的高介电常数（高k）栅极电介质和非易失性随机存取存储器（NVRAM）器件的高k隧道电介质。 随后沉积至少一个导电材料层，控制栅极电介质层和一次性材料层的堆叠并且被光刻图案化。 沉积并图案化平坦化介电层，并且去除一次性材料部分。 控制栅极电介质层的剩余部分保留在NVRAM器件区域中，但在FET区域中被去除。 导电材料沉积在栅极腔中以为NVRAM器件提供控制栅极和用于FET的栅极部分。 或者，控制栅介质层可以用NVRAM器件区域中的高k控制栅极电介质代替。

    GATE OXIDE FOR NANOSHEET TRANSISTOR DEVICES
    9.
    发明申请
    GATE OXIDE FOR NANOSHEET TRANSISTOR DEVICES 有权

    公开(公告)号：US20210217873A1

    公开(公告)日：2021-07-15

    申请号：US16742295

    申请日：2020-01-14

    申请人： International Business Machines Corporation

    发明人： Shahab Siddiqui ,  Koji Watanabe ,  Charlotte DeWan Adams ,  Kai Zhao ,  Daniel James Dechene ,  Rishikesh Krishnan

    IPC分类号： H01L29/66 ,  H01L29/417 ,  H01L29/423 ,  H01L29/786 ,  H01L21/02 ,  H01L21/8234

    摘要： A method of forming a semiconductor structure includes forming a first nanosheet stack and a second nanosheet stack on a semiconductor substrate. The first nanosheet stack includes a plurality of alternating first sacrificial layers and first channel layers. The first sacrificial layers each define a first sacrificial height. The second nanosheet stack includes a plurality of alternating second sacrificial layers and second channel layers. The second sacrificial layers each define a second sacrificial height greater than the first sacrificial height of the first sacrificial layers. The method further includes removing the first and second sacrificial layers respectively from the first and second nanosheet stacks. A metal gate is deposited over the first and second nanosheet stacks to form respective first and second nanosheet transistor structures.