公开(公告)号：US20130161618A1

公开(公告)日：2013-06-27

申请号：US13772402

申请日：2013-02-21

Applicant: International Business Machines Corporation

Inventor： Alan B. Botula ,  John J. Ellis-Monaghan ,  Alvin J. Joseph ,  Max G. Levy ,  Richard A. Phelps ,  James A. Slinkman ,  Randy L. Wolf

IPC: H01L29/04 ,  H01L21/02

CPC classification number: H01L21/02488 ,  H01L21/2652 ,  H01L21/7624 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/78603

Abstract: Disclosed is semiconductor structure with an insulator layer on a semiconductor substrate and a device layer is on the insulator layer. The substrate is doped with a relatively low dose of a dopant having a given conductivity type such that it has a relatively high resistivity. Additionally, a portion of the semiconductor substrate immediately adjacent to the insulator layer can be doped with a slightly higher dose of the same dopant, a different dopant having the same conductivity type or a combination thereof. Optionally, micro-cavities are created within this same portion so as to balance out any increase in conductivity due to increased doping with a corresponding increase in resistivity. Increasing the dopant concentration at the semiconductor substrate-insulator layer interface raises the threshold voltage (Vt) of any resulting parasitic capacitors and, thereby reduces harmonic behavior. Also disclosed herein are embodiments of a method for forming such a semiconductor structure.

Abstract translation: 公开了在半导体衬底上具有绝缘体层并且器件层位于绝缘体层上的半导体结构。 衬底掺杂有相对低剂量的具有给定导电类型的掺杂剂，使得其具有相对高的电阻率。 此外，与绝缘体层紧密相邻的半导体衬底的一部分可掺杂略高的相同掺杂剂剂量，具有相同导电类型的不同掺杂剂或其组合。 可选地，在该相同部分内形成微腔，以便平衡由于掺杂增加导致的电导率的增加，同时具有相应的电阻率增加。 增加半导体衬底 - 绝缘体层界面处的掺杂剂浓度会提高任何结果的寄生电容器的阈值电压（Vt），从而降低谐波行为。 本文还公开了用于形成这种半导体结构的方法的实施例。

公开(公告)号：US09997385B2

公开(公告)日：2018-06-12

申请号：US15490175

申请日：2017-04-18

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Shawn A. Adderly ,  Samantha D. DiStefano ,  Jeffrey P. Gambino ,  Max G. Levy ,  Max L. Lifson ,  Matthew D. Moon ,  Timothy D. Sullivan

IPC: H01L21/67 ,  G01S15/42 ,  G01B17/00

CPC classification number: H01L21/67259 ,  G01B17/00 ,  G01S15/42 ,  H01L21/68 ,  Y10T29/49764 ,  Y10T279/21

Abstract: An apparatus and an associated method. The apparatus includes a chuck in a process chamber, an array of three or more ultrasonic sensors in the process chamber, a ceramic ring surrounding the chuck, and a controller connected to the ultrasonic sensors. The chuck is configured to removeably hold a substrate for processing. Each ultrasonic sensor may send a respective ultrasonic sound wave to a respective preselected peripheral region of the substrate and receive a respective return ultrasonic sound wave from the preselected peripheral region. The controller may compare a measured position of the substrate on the chuck to a specified placement of the substrate on the chuck based on a measured elapsed time between sending the ultrasonic sound wave and receiving the return ultrasonic sound wave for each ultrasonic sensor. The method compares a measured position of the substrate on the chuck to a specified position on the chuck.

公开(公告)号：US09825119B2

公开(公告)日：2017-11-21

申请号：US15226185

申请日：2016-08-02

Applicant: International Business Machines Corporation

Inventor： Max G. Levy ,  Gary L. Milo ,  David C. Thomas

IPC: H01L21/31 ,  H01L49/02 ,  H01L21/311 ,  H01L21/3213 ,  H01L21/768

CPC classification number: H01L28/87 ,  H01L21/31144 ,  H01L21/32139 ,  H01L21/76895

Abstract: Embodiments disclose a method of fabrication and a semiconductor structure comprising a Metal-insulator-metal (MIM) capacitor. The method of fabrication includes depositing a first conductive material on a semiconductor substrate. A first dielectric material is deposited on the first conductive material. A second conductive material is deposited on the first dielectric material. The top plate is formed by etching the second conductive material. The bottom plate is formed by etching a portion of the first conductive material. At least one opening is formed in the first dielectric layer down to the first conductive material.

公开(公告)号：US20160343797A1

公开(公告)日：2016-11-24

申请号：US15226185

申请日：2016-08-02

Applicant: International Business Machines Corporation

Inventor： Max G. Levy ,  Gary L. Milo ,  David C. Thomas

IPC: H01L49/02 ,  H01L21/3213 ,  H01L21/311 ,  H01L21/768

CPC classification number: H01L28/87 ,  H01L21/31144 ,  H01L21/32139 ,  H01L21/76895

Abstract: Embodiments disclose a method of fabrication and a semiconductor structure comprising a Metal-insulator-metal (MIM) capacitor. The method of fabrication includes depositing a first conductive material on a semiconductor substrate. A first dielectric material is deposited on the first conductive material. A second conductive material is deposited on the first dielectric material. The top plate is formed by etching the second conductive material. The bottom plate is formed by etching a portion of the first conductive material. At least one opening is formed in the first dielectric layer down to the first conductive material.

公开(公告)号：US20140327084A1

公开(公告)日：2014-11-06

申请号：US13874922

申请日：2013-05-01

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Natalie B. Feilchenfeld ,  Max G. Levy ,  Richard A. Phelps ,  Santosh Sharma ,  Yun Shi ,  Michael J. Zierak

IPC: H01L29/06 ,  H01L21/762

CPC classification number: H01L29/0653 ,  H01L21/76232 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/42368 ,  H01L29/66681 ,  H01L29/7816 ,  H01L29/7846

Abstract: Various embodiments include field effect transistor (FET) structures and methods of forming such structures. In various embodiments, an FET structure includes: a deep n-type well; an shallow n-type well and a p-type well each within the deep n-type well; and a shallow trench isolation (STI) region within the shallow n-type well, the STI region including: a first section having a first depth within the shallow n-type well as measured from an upper surface of the shallow n-type well; and a second section contacting and overlying the first section, the second section having a second depth within the shallow n-type well as measured from the upper surface of the shallow n-type well.

Abstract translation: 各种实施例包括场效应晶体管（FET）结构和形成这种结构的方法。 在各种实施例中，FET结构包括：深n型阱; 深n型井内的浅n型井和p型井; 以及在浅n型阱内的浅沟槽隔离（STI）区域，所述STI区域包括：从浅n型阱的上表面测量的，在浅n型阱内具有第一深度的第一部分; 以及与所述第一部分接触并覆盖的第二部分，所述第二部分具有从所述浅n型阱的上表面测量的所述浅n型阱内的第二深度。