公开(公告)号：US09362229B2

公开(公告)日：2016-06-07

申请号：US14515925

申请日：2014-10-16

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Jeffrey P. Gambino ,  David L. Harame ,  Baozhen Li ,  Timothy D. Sullivan ,  Bjorn K. A. Zetterlund

IPC: H01L23/528 ,  H01L23/532 ,  H01L21/768 ,  H01L23/522

CPC classification number: H01L23/53238 ,  H01L21/76843 ,  H01L23/5226 ,  H01L23/528 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Semiconductor devices with enhanced electromigration performance and methods of manufacture are disclosed. The method includes forming at least one metal line in electrical contact with a device. The method further includes forming at least one staple structure in electrical contact with the at least one metal line. The at least one staple structure is formed such that electrical current passing through the at least one metal line also passes through the at least staple structure to reduce electromigration issues.

Abstract translation: 公开了具有增强的电迁移性能和制造方法的半导体器件。 该方法包括形成与装置电接触的至少一个金属线。 该方法还包括形成与至少一个金属线电接触的至少一个钉结构。 形成至少一个钉结构，使得通过至少一个金属线的电流也穿过至少缝合结构以减少电迁移问题。

公开(公告)号：US20150331014A1

公开(公告)日：2015-11-19

申请号：US14276223

申请日：2014-05-13

Applicant: International Business Machines Corporation

Inventor： David M. Audette ,  Dennis M. Bronson, JR. ,  Joseph K. V. Comeau ,  Dustin M. Fregeau ,  David L. Gardell ,  Frederick H. Roy, III ,  James R. Salimeno, III ,  Timothy D. Sullivan

IPC: G01R1/073 ,  G01R31/28

CPC classification number: G01R3/00 ,  G01R1/06738 ,  G01R1/07314 ,  G01R1/07342 ,  G01R31/2886

Abstract: A probe tip structure that decreases the accumulation rate of Sn particles to the probe tip and enables considerably more efficient and complete laser cleaning is disclosed. In an embodiment, the probe structure includes an array of probe tips, each probe tip having an inner core; an interfacial layer bonded to the inner core; and an outer layer bonded to the interfacial layer, wherein the outer layer is resistant to adherence of the solder of the ball grid array package.

Abstract translation: 公开了一种探针尖端结构，其降低了Sn颗粒到探针尖端的累积速率，并且能够实现更有效和更完整的激光清洗。 在一个实施例中，探针结构包括探针尖端的阵列，每个探针尖端具有内核; 接合到内芯的界面层; 以及结合到所述界面层的外层，其中所述外层抵抗所述球栅阵列封装的焊料的粘附。

公开(公告)号：US09165850B2

公开(公告)日：2015-10-20

申请号：US14525682

申请日：2014-10-28

Applicant: International Business Machines Corporation

Inventor： Timothy H. Daubenspeck ,  Jeffrey P. Gambino ,  Christopher D. Muzzy ,  Wolfgang Sauter ,  Timothy D. Sullivan

IPC: H01L23/31 ,  H01L23/00 ,  H01L23/525

CPC classification number: H01L23/3114 ,  H01L23/3192 ,  H01L23/525 ,  H01L23/562 ,  H01L24/05 ,  H01L24/06 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L2224/02125 ,  H01L2224/0231 ,  H01L2224/02331 ,  H01L2224/0236 ,  H01L2224/02381 ,  H01L2224/0239 ,  H01L2224/024 ,  H01L2224/0401 ,  H01L2224/05569 ,  H01L2224/05572 ,  H01L2224/05573 ,  H01L2224/05575 ,  H01L2224/05618 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05655 ,  H01L2224/05671 ,  H01L2224/06102 ,  H01L2224/11848 ,  H01L2224/13147 ,  H01L2224/16225 ,  H01L2924/00014 ,  H01L2924/07025 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15174 ,  H01L2924/1531 ,  H01L2924/15311 ,  H01L2924/3511 ,  H01L2224/05552 ,  H01L2924/00

Abstract: Structures and methods of making a flip chip package that employ polyimide pads of varying heights at a radial distance from a center of an integrated circuit (IC) chip for a flip chip package. The polyimide pads may be formed under electrical connectors, which connect the IC chip to a chip carrier of the flip chip package, so that electrical connectors formed on polyimide pads of greater height are disposed at a greater radial distance from the center of the IC chip, while electrical connectors formed on polyimide pads of a lesser height are disposed more proximately to the center of the IC chip. Electrical connectors of a greater relative height to the IC chip's surface may compensate for a gap, produced by heat-induced warpage during the making of the flip chip package, that separates the electrical connectors on the IC chip from flip chip attaches on the chip carrier.

Abstract translation: 制造倒装芯片封装的结构和方法，其采用距离用于倒装芯片封装的集成电路（IC）芯片的中心的径向距离的不同高度的聚酰亚胺焊盘。 聚酰亚胺焊盘可以形成在电连接器下面，电连接器将IC芯片连接到倒装芯片封装的芯片载体，使得形成在更高高度的聚酰亚胺焊盘上的电连接器设置在离IC芯片中心更大的径向距离处 而形成在较低高度的聚酰亚胺焊盘上的电连接器更靠近IC芯片的中心设置。 与IC芯片表面相对高的电连接器可以补偿在制造倒装芯片封装期间由热引起的翘曲产生的间隙，其将IC芯片上的电连接器与芯片载体上的倒装芯片分离 。

公开(公告)号：US09087839B2

公开(公告)日：2015-07-21

申请号：US13853301

申请日：2013-03-29

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Shawn A. Adderly ,  Daniel A. Delibac ,  Zhong-Xiang He ,  Matthew D. Moon ,  Anthony C. Speranza ,  Timothy D. Sullivan ,  David C. Thomas ,  Eric J. White

IPC: H01L21/20 ,  H01L23/522 ,  H01L49/02 ,  H01L23/532

CPC classification number: H01L23/5223 ,  H01L23/53223 ,  H01L28/60 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Disclosed are semiconductor structures with metal lines and methods of manufacture which reduce or eliminate extrusion formation. The method includes forming a metal wiring comprising a layered structure of metal materials with an upper constraining layer. The method further includes forming a film on the metal wiring which prevents metal extrusion during an annealing process.

Abstract translation: 公开了具有金属线的半导体结构和制造方法，其减少或消除挤出形成。 该方法包括形成金属布线，该金属布线包括具有上部约束层的金属材料的层状结构。 该方法还包括在金属布线上形成膜，该膜在退火过程中防止金属挤出。

公开(公告)号：US20150089805A1

公开(公告)日：2015-04-02

申请号：US14043047

申请日：2013-10-01

Applicant: International Business Machines Corporation

Inventor： Stephen P. Ayotte ,  Glen E. Richard ,  Timothy D. Sullivan ,  Timothy M. Sullivan

IPC: H05K3/34 ,  B23K1/002 ,  B23K1/00

CPC classification number: B23K1/002 ,  B23K1/0016 ,  H05K3/3436 ,  H05K3/3494 ,  H05K2203/101 ,  Y10T29/49144 ,  Y10T29/53178

Abstract: Methods and apparatus for joining a chip with a substrate. The chip is moved by with a pick-and-place machine from a first location to a second location proximate to the substrate over a first time. In response to moving the chip in a motion path from the first location to the second location, a plurality of solder bumps carried on the chip are liquefied over a second time that is less than the first time. While the solder bumps are liquefied, the chip is placed by the pick-and-place machine onto the substrate.

Abstract translation: 将芯片与基板接合的方法和装置。 芯片通过拾取和放置机器在第一时间从第一位置移动到靠近基板的第二位置。 响应于将芯片从第一位置移动到第二位置的运动路径，在芯片上承载的多个焊料凸块第二次液化，该第二次小于第一次。 当焊料凸块液化时，芯片由拾取和放置机器放置在基板上。

公开(公告)号：US20140187034A1

公开(公告)日：2014-07-03

申请号：US14200613

申请日：2014-03-07

Applicant: International Business Machines Corporation

Inventor： Timothy H. Daubenspeck ,  Jeffrey P. Gambino ,  Christopher D. Muzzy ,  Wolfgang Sauter ,  Timothy D. Sullivan

IPC: H01L23/00

CPC classification number: H01L24/11 ,  H01L23/49816 ,  H01L24/13 ,  H01L24/81 ,  H01L2224/1147 ,  H01L2224/11901 ,  H01L2224/11902 ,  H01L2224/13018 ,  H01L2224/13019 ,  H01L2224/13023 ,  H01L2224/13076 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/1357 ,  H01L2224/136 ,  H01L2224/13609 ,  H01L2224/13611 ,  H01L2224/13613 ,  H01L2224/13618 ,  H01L2224/1362 ,  H01L2224/13639 ,  H01L2224/13647 ,  H01L2224/1601 ,  H01L2224/16237 ,  H01L2224/81191 ,  H01L2224/81193 ,  H01L2224/81801 ,  H01L2924/00013 ,  H01L2924/01005 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01051 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/351 ,  H01L2924/00014 ,  H01L2924/01028 ,  H01L2224/13099 ,  H01L2924/00012

Abstract: Disclosed is a chip and method of forming the chip with improved conductive pads that allow for flexible C4 connections with a chip carrier or with another integrated circuit chip. The pads have a three-dimensional geometric shape (e.g., a pyramid or cone shape) with a base adjacent to the surface of the chip, a vertex opposite the base and, optionally, mushroom-shaped cap atop the vertex. Each pad can include a single layer of conductive material or multiple layers of conductive material (e.g., a wetting layer stacked above a non-wetting layer). The pads can be left exposed to allow for subsequent connection to corresponding solder bumps on a chip carrier or a second chip. Alternatively, solder balls can be positioned on the conductive pads to allow for subsequent connection to corresponding solder-paste filled openings on a chip carrier or a second chip.

Abstract translation: 公开了一种用改进的导电焊盘形成芯片的芯片和方法，其允许与芯片载体或另一个集成电路芯片的柔性C4连接。 垫具有三维几何形状（例如，金字塔或锥形），其具有与芯片表面相邻的基部，与基部相对的顶点以及可选地在顶点顶部的蘑菇形帽。 每个焊盘可以包括单层导电材料或多层导电材料（例如，堆叠在非润湿层上方的润湿层）。 焊盘可以被暴露以允许随后连接到芯片载体或第二芯片上的相应焊料凸块。 或者，焊球可以定位在导电焊盘上，以允许随后连接到芯片载体或第二芯片上相应的焊膏填充的开口。

公开(公告)号：US20140038381A1

公开(公告)日：2014-02-06

申请号：US14048629

申请日：2013-10-08

Applicant: International Business Machines Corporation

Inventor： Joseph M. Lukaitis ,  Deborah M. Massey ,  Timothy D. Sullivan ,  Ping-Chuan Wang ,  Kimball M. Watson

IPC: H01L49/02

CPC classification number: H01L28/20 ,  H01L23/3677 ,  H01L23/5228 ,  H01L27/0211 ,  H01L28/24 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A structure and method of fabricating the structure includes a semiconductor substrate having a top surface defining a horizontal direction and a plurality of interconnect levels stacked from a lowermost level proximate the top surface of the semiconductor substrate to an uppermost level furthest from the top surface. Each of the interconnect levels include vertical metal conductors physically connected to one another in a vertical direction perpendicular to the horizontal direction. The vertical conductors in the lowermost level being physically connected to the top surface of the substrate, and the vertical conductors forming a heat sink connected to the semiconductor substrate. A resistor is included in a layer immediately above the uppermost level. The vertical conductors being aligned under a downward vertical resistor footprint of the resistor, and each interconnect level further include horizontal metal conductors positioned in the horizontal direction and being connected to the vertical conductors.

Abstract translation: 制造该结构的结构和方法包括：半导体衬底，其具有限定水平方向的顶表面和从最接近半导体衬底的顶表面的最底层到距离顶表面最远的最高水平层叠的多个互连层。 每个互连层包括在垂直于水平方向的垂直方向上彼此物理连接的垂直金属导体。 最底层的垂直导体物理地连接到衬底的顶表面，垂直导体形成连接到半导体衬底的散热片。 一个电阻器被包含在最上层的上方的层中。 垂直导体在电阻器的向下垂直电阻器占位面下对准，并且每个互连级别还包括位于水平方向上并且连接到垂直导体的水平金属导体。

公开(公告)号：US10794948B2

公开(公告)日：2020-10-06

申请号：US15805377

申请日：2017-11-07

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Fen Chen ,  Mukta G. Farooq ,  John A. Griesemer ,  Chandrasekaran Kothandaraman ,  John M. Safran ,  Timothy D. Sullivan ,  Ping-Chuan Wang ,  Lijuan Zhang

IPC: H01L21/66 ,  G01R31/08 ,  H01L23/48 ,  G01R31/28

Abstract: An EM testing method includes forcing electrical current through EM monitor wiring arranged in close proximity to the perimeter of the TSV and measuring an electrical resistance drop across the EM monitor wiring. The method may further include determining if an electrical short exists between the EM monitor wiring and the TSV from the measured electrical resistance. The method may further include determining if an early electrical open or resistance increase exists within the EM monitoring wiring due to TSV induced proximity effect.

公开(公告)号：US09997385B2

公开(公告)日：2018-06-12

申请号：US15490175

申请日：2017-04-18

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Shawn A. Adderly ,  Samantha D. DiStefano ,  Jeffrey P. Gambino ,  Max G. Levy ,  Max L. Lifson ,  Matthew D. Moon ,  Timothy D. Sullivan

IPC: H01L21/67 ,  G01S15/42 ,  G01B17/00

CPC classification number: H01L21/67259 ,  G01B17/00 ,  G01S15/42 ,  H01L21/68 ,  Y10T29/49764 ,  Y10T279/21

Abstract: An apparatus and an associated method. The apparatus includes a chuck in a process chamber, an array of three or more ultrasonic sensors in the process chamber, a ceramic ring surrounding the chuck, and a controller connected to the ultrasonic sensors. The chuck is configured to removeably hold a substrate for processing. Each ultrasonic sensor may send a respective ultrasonic sound wave to a respective preselected peripheral region of the substrate and receive a respective return ultrasonic sound wave from the preselected peripheral region. The controller may compare a measured position of the substrate on the chuck to a specified placement of the substrate on the chuck based on a measured elapsed time between sending the ultrasonic sound wave and receiving the return ultrasonic sound wave for each ultrasonic sensor. The method compares a measured position of the substrate on the chuck to a specified position on the chuck.

公开(公告)号：US20180074111A1

公开(公告)日：2018-03-15

申请号：US15805406

申请日：2017-11-07

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Fen Chen ,  Mukta G. Farooq ,  John A. Griesemer ,  Chandrasekaran Kothandaraman ,  John M. Safran ,  Timothy D. Sullivan ,  Ping-Chuan Wang ,  Lijuan Zhang

IPC: G01R31/08 ,  H01L21/66 ,  H01L23/48

CPC classification number: G01R31/08 ,  G01R31/2856 ,  G01R31/2858 ,  H01L22/14 ,  H01L22/34 ,  H01L23/481 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A structure, such as a wafer, semiconductor chip, integrated circuit, or the like, includes a through silicon via (TSV) and an electromigration (EM) monitor. The TSV) incldues at least one perimeter sidewall. The EM monitor includes a first EM wire separated from the perimeter sidewall of the TSV by a dielectric