公开(公告)号：US09087839B2

公开(公告)日：2015-07-21

申请号：US13853301

申请日：2013-03-29

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Shawn A. Adderly ,  Daniel A. Delibac ,  Zhong-Xiang He ,  Matthew D. Moon ,  Anthony C. Speranza ,  Timothy D. Sullivan ,  David C. Thomas ,  Eric J. White

IPC: H01L21/20 ,  H01L23/522 ,  H01L49/02 ,  H01L23/532

CPC classification number: H01L23/5223 ,  H01L23/53223 ,  H01L28/60 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Disclosed are semiconductor structures with metal lines and methods of manufacture which reduce or eliminate extrusion formation. The method includes forming a metal wiring comprising a layered structure of metal materials with an upper constraining layer. The method further includes forming a film on the metal wiring which prevents metal extrusion during an annealing process.

Abstract translation: 公开了具有金属线的半导体结构和制造方法，其减少或消除挤出形成。 该方法包括形成金属布线，该金属布线包括具有上部约束层的金属材料的层状结构。 该方法还包括在金属布线上形成膜，该膜在退火过程中防止金属挤出。

公开(公告)号：US09330988B1

公开(公告)日：2016-05-03

申请号：US14580283

申请日：2014-12-23

Applicant: International Business Machines Corporation

Inventor： Shawn A. Adderly ,  Kyle Babinski ,  Daniel A. Delibac ,  David A. DeMuynck ,  Shawn R. Goddard ,  Matthew D. Moon ,  Melissa J. Roma ,  Craig E. Schneider

IPC: H01L21/66 ,  H01L21/3213

CPC classification number: H01L22/22 ,  H01L21/3065 ,  H01L21/3086 ,  H01L21/31116 ,  H01L21/32136 ,  H01L21/32139 ,  H01L22/12 ,  H01L22/20

Abstract: Disclosed is a method of manufacturing integrated circuit (IC) chips. In the method, wafers are received and the backside roughness levels of these wafers are determined. Based on the backside roughness levels, the wafers are sorted into different groups. Chips having the same design are manufactured on wafers from all of the different groups. However, during manufacturing, process(es) is/are performed differently on wafers from one or more of the different groups to minimize systematic variations in a specific parameter (e.g., wire width) in the resulting chips. Specifically, because systematic variations may occur when the exact same processes are used to form IC chips on wafers with different backside roughness levels, the method disclosed herein selectively adjusts one or more of those processes when performed on wafers from one or more of the different groups to ensure that the specific parameter is approximately equal in the resulting integrated IC chips.

Abstract translation: 公开了一种制造集成电路（IC）芯片的方法。 在该方法中，接收晶片并确定这些晶片的背面粗糙度水平。 基于背面粗糙度水平，将晶片分成不同的组。 具有相同设计的芯片在来自所有不同组的晶片上制造。 然而，在制造过程中，在来自一个或多个不同组的晶片上进行不同的处理，以最小化所得芯片中的特定参数（例如，线宽）的系统变化。 具体地说，因为当使用完全相同的工艺在具有不同背面粗糙度水平的晶片上形成IC芯片时，可能发生系统的变化，所以当在一个或多个不同的组中对晶片执行时，这里所公开的方法选择性地调节这些工艺中的一个或多个 以确保在所得到的集成IC芯片中的具体参数近似相等。

公开(公告)号：US09275868B2

公开(公告)日：2016-03-01

申请号：US13946456

申请日：2013-07-19

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Shawn A. Adderly ,  Jeffrey P. Gambino ,  Max L. Lifson ,  Matthew D. Moon ,  William J. Murphy ,  Timothy D. Sullivan ,  David C. Thomas

IPC: H01L21/308 ,  H01L21/306 ,  H01L21/3065

CPC classification number: H01L21/30604 ,  H01L21/3065 ,  H01L21/3083

Abstract: Substrates (wafers) with uniform backside roughness and methods of manufacture are disclosed. The method includes forming a material on a backside of a wafer. The method further includes patterning the material to expose portions of the backside of the wafer. The method further includes roughening the backside of the wafer through the patterned material to form a uniform roughness.

Abstract translation: 公开了具有均匀背面粗糙度的基板（晶片）和制造方法。 该方法包括在晶片的背面形成材料。 该方法还包括图案化材料以暴露晶片背面的部分。 该方法还包括通过图案化材料粗糙化晶片的背面以形成均匀的粗糙度。

公开(公告)号：US09997385B2

公开(公告)日：2018-06-12

申请号：US15490175

申请日：2017-04-18

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Shawn A. Adderly ,  Samantha D. DiStefano ,  Jeffrey P. Gambino ,  Max G. Levy ,  Max L. Lifson ,  Matthew D. Moon ,  Timothy D. Sullivan

IPC: H01L21/67 ,  G01S15/42 ,  G01B17/00

CPC classification number: H01L21/67259 ,  G01B17/00 ,  G01S15/42 ,  H01L21/68 ,  Y10T29/49764 ,  Y10T279/21

Abstract: An apparatus and an associated method. The apparatus includes a chuck in a process chamber, an array of three or more ultrasonic sensors in the process chamber, a ceramic ring surrounding the chuck, and a controller connected to the ultrasonic sensors. The chuck is configured to removeably hold a substrate for processing. Each ultrasonic sensor may send a respective ultrasonic sound wave to a respective preselected peripheral region of the substrate and receive a respective return ultrasonic sound wave from the preselected peripheral region. The controller may compare a measured position of the substrate on the chuck to a specified placement of the substrate on the chuck based on a measured elapsed time between sending the ultrasonic sound wave and receiving the return ultrasonic sound wave for each ultrasonic sensor. The method compares a measured position of the substrate on the chuck to a specified position on the chuck.

公开(公告)号：US20150140809A1

公开(公告)日：2015-05-21

申请号：US14600273

申请日：2015-01-20

Applicant: International Business Machines Corporation

Inventor： David A. DeMuynck ,  Zhong-Xiang He ,  Daniel R. Miga ,  Matthew D. Moon ,  Daniel S. Vanslette ,  Eric J. White

IPC: H01L21/768

CPC classification number: H01L21/76843 ,  H01L21/76802 ,  H01L21/76834 ,  H01L21/76846 ,  H01L21/76879 ,  H01L23/5227 ,  H01L28/10 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The disclosure relates generally to integrated circuits (IC), IC interconnects, and methods of fabricating the same, and more particularly, high performance inductors. The IC includes at least one trench within a dielectric layer disposed on a substrate. The trench is conformally coated with a liner and seed layer, and includes an interconnect within. The interconnect includes a hard mask on the sidewalls of the interconnect.

Abstract translation: 本公开一般涉及集成电路（IC），IC互连及其制造方法，更具体地，涉及高性能电感器。 IC包括设置在基板上的电介质层内的至少一个沟槽。 沟槽被保形地涂覆有衬里和种子层，并且包括内部的互连。 互连包括在互连的侧壁上的硬掩模。

公开(公告)号：US20150255395A1

公开(公告)日：2015-09-10

申请号：US14718466

申请日：2015-05-21

Applicant: International Business Machines Corporation

Inventor： Max G. Levy ,  Gary L. Milo ,  Matthew D. Moon ,  Anthony C. Speranza ,  Timothy D. Sullivan ,  David C. Thomas ,  Steven S. Williams

IPC: H01L23/528 ,  H01L49/02 ,  H01L23/532

CPC classification number: H01L23/5283 ,  H01L21/76883 ,  H01L23/5223 ,  H01L23/528 ,  H01L23/53214 ,  H01L23/53223 ,  H01L28/60 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Aspects of the present invention relate to a controlled metal extrusion opening in a semiconductor structure. Various embodiments include a semiconductor structure. The structure includes an aluminum layer. The aluminum layer includes an aluminum island within the aluminum layer, and a lateral extrusion receiving opening extending through the aluminum layer adjacent the aluminum island. The opening includes a lateral extrusion of the aluminum layer of the semiconductor structure. Additional embodiments include a method of forming a semiconductor structure. The method can include forming an aluminum layer over a titanium layer. The aluminum layer includes an aluminum island within the aluminum layer. The method can also include forming an opening extending through the aluminum layer adjacent the aluminum island within the aluminum layer. The opening includes a lateral extrusion of the aluminum layer of the semiconductor layer.

Abstract translation: 本发明的方面涉及半导体结构中的受控金属挤压开口。 各种实施例包括半导体结构。 该结构包括铝层。 铝层包括在铝层内的铝岛，以及横向挤压接收开口，其延伸穿过靠近铝岛的铝层。 该开口包括半导体结构的铝层的横向挤压。 另外的实施例包括形成半导体结构的方法。 该方法可以包括在钛层上形成铝层。 铝层包括铝层内的铝岛。 该方法还可以包括在铝层内形成延伸穿过邻近铝岛的铝层的开口。 该开口包括半导体层的铝层的侧向挤压。

公开(公告)号：US20150235881A1

公开(公告)日：2015-08-20

申请号：US14183631

申请日：2014-02-19

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Shawn A. Adderly ,  Samantha D. DiStefano ,  Jeffrey P. Gambino ,  Max G. Levy ,  Max L. Lifson ,  Matthew D. Moon ,  Timothy D. Sullivan

IPC: H01L21/67 ,  H01L21/68 ,  H01L21/683

CPC classification number: H01L21/67259 ,  G01B17/00 ,  G01S15/42 ,  H01L21/68 ,  Y10T29/49764 ,  Y10T279/21

Abstract: An apparatus and method for centering substrates determining on a chuck. The apparatus includes a chuck in a process chamber, the chuck configured to removeably hold a substrate for processing; an array of two or more ultrasonic sensors arranged in the process chamber, each ultrasonic sensor arranged relative to the chuck so as to send a respective ultrasonic sound wave to a respective preselected region of the substrate and receive a respective return ultrasonic sound wave from the preselected region of the substrate; and a controller connected to each ultrasonic sensor and configured to compare a measured position of the substrate on the chuck to a specified placement of the substrate on the chuck based on a measured elapsed time between sending the ultrasonic sound wave and receiving the return ultrasonic sound wave from each ultrasonic sensor.

Abstract translation: 一种用于使确定在卡盘上的基板居中的装置和方法。 该装置包括处理室中的卡盘，卡盘构造成可移除地保持用于处理的基板; 布置在处理室中的两个或更多个超声波传感器的阵列，每个超声波传感器相对于卡盘布置，以便将相应的超声波发送到基板的各个预选区域，并从预选的接收相应的返回超声波 基底区域; 以及控制器，其连接到每个超声波传感器，并且被配置为基于在发送所述超声波和接收所述返回超声波之间的测量的经过时间来比较所述卡盘上的所述基板的测量位置与所述基板在所述卡盘上的指定布置 从每个超声波传感器。

公开(公告)号：US09006703B2

公开(公告)日：2015-04-14

申请号：US13955531

申请日：2013-07-31

Applicant: International Business Machines Corporation

Inventor： Shawn A. Adderly ,  Brian M. Czabaj ,  Daniel A. Delibac ,  Jeffrey P. Gambino ,  Matthew D. Moon ,  David C. Thomas

IPC: H01L21/00 ,  H01L49/02 ,  H01L21/66

CPC classification number: H01L28/40 ,  H01L22/12 ,  H01L22/20

Abstract: Aspects of the present invention relate to method for reducing lateral extrusion formed in semiconductor structures and semiconductor structures formed thereof. Various embodiments include a method for reducing lateral extrusion formed in semiconductor structures. The method can include removing a portion of a first lateral extrusion in an aluminum layer of the semiconductor structure, and determining a post-removal thickness of a dielectric layer positioned adjacent the aluminum layer. The post-removal thickness may be determined subsequent to the removing of the portion of the first lateral extrusion. The method can also include determining a difference between the post-removal thickness of the dielectric layer and a pre-removal thickness of the dielectric layer.

Abstract translation: 本发明的方面涉及减少由半导体结构形成的侧向挤出和由其形成的半导体结构的方法。 各种实施例包括用于减少在半导体结构中形成的横向挤压的方法。 该方法可以包括去除半导体结构的铝层中的第一侧向挤压的一部分，以及确定位于铝层附近的电介质层的去除后厚度。 去除后厚度可以在去除第一侧向挤出部分的部分之后确定。 该方法还可以包括确定介电层的去除后厚度与介电层的去除去除厚度之间的差异。

公开(公告)号：US20150035117A1

公开(公告)日：2015-02-05

申请号：US13955531

申请日：2013-07-31

Applicant: International Business Machines Corporation

Inventor： Shawn A. Adderly ,  Brian M. Czabaj ,  Daniel A. Delibac ,  Jeffrey P. Gambino ,  Matthew D. Moon ,  David C. Thomas

IPC: H01L49/02 ,  H01L21/66

CPC classification number: H01L28/40 ,  H01L22/12 ,  H01L22/20

Abstract: Aspects of the present invention relate to method for reducing lateral extrusion formed in semiconductor structures and semiconductor structures formed thereof. Various embodiments include a method for reducing lateral extrusion formed in semiconductor structures. The method can include removing a portion of a first lateral extrusion in an aluminum layer of the semiconductor structure, and determining a post-removal thickness of a dielectric layer positioned adjacent the aluminum layer. The post-removal thickness may be determined subsequent to the removing of the portion of the first lateral extrusion. The method can also include determining a difference between the post-removal thickness of the dielectric layer and a pre-removal thickness of the dielectric layer.

Abstract translation: 本发明的方面涉及减少由半导体结构形成的侧向挤出和由其形成的半导体结构的方法。 各种实施例包括用于减少在半导体结构中形成的横向挤压的方法。 该方法可以包括去除半导体结构的铝层中的第一侧向挤压的一部分，以及确定位于铝层附近的电介质层的去除后厚度。 去除后厚度可以在去除第一侧向挤出部分的部分之后确定。 该方法还可以包括确定介电层的去除后厚度与介电层的去除去除厚度之间的差异。

公开(公告)号：US10224225B2

公开(公告)日：2019-03-05

申请号：US15957111

申请日：2018-04-19

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Shawn A. Adderly ,  Samantha D. DiStefano ,  Jeffrey P. Gambino ,  Max G. Levy ,  Max L. Lifson ,  Matthew D. Moon ,  Timothy D. Sullivan

IPC: H01L21/67 ,  H01L21/68 ,  H01L21/683 ,  G01B17/00 ,  G01S15/42

Abstract: An apparatus and an associated method. The apparatus includes a chuck, an array of three or more ultrasonic sensors, a ceramic ring surrounding the chuck, and a controller connected to the ultrasonic sensors. The chuck is configured to removeably hold a substrate for processing. Each ultrasonic sensor may send a respective ultrasonic sound wave to a respective preselected peripheral region of the substrate and receive a respective return ultrasonic sound wave from the preselected peripheral region. The controller may compare a measured position of the substrate on the chuck to a specified placement of the substrate on the chuck based on a measured elapsed time between sending the ultrasonic sound wave and receiving the return ultrasonic sound wave for each ultrasonic sensor. The method compares a measured position of the substrate on the chuck to a specified position on the chuck.