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    EFFICIENT TILE MAPPING FOR ROW-BY-ROW CONVOLUTIONAL NEURAL NETWORK MAPPING FOR ANALOG ARTIFICIAL INTELLIGENCE NETWORK INFERENCE
    22.
    发明申请
    EFFICIENT TILE MAPPING FOR ROW-BY-ROW CONVOLUTIONAL NEURAL NETWORK MAPPING FOR ANALOG ARTIFICIAL INTELLIGENCE NETWORK INFERENCE 有权

    公开(公告)号：US20230100139A1

    公开(公告)日：2023-03-30

    申请号：US18061074

    申请日：2022-12-02

    申请人： International Business Machines Corporation

    发明人： HsinYu Tsai ,  Geoffrey Burr ,  Pritish Narayanan

    IPC分类号： G06N3/08

    摘要： Implementing a convolutional neural network (CNN) includes configuring a crosspoint array to implement a convolution layer in the CNN. Convolution kernels of the layer are stored in crosspoint devices of the array. Computations for the CNN are performed by iterating a set of operations for a predetermined number of times. The operations include transmitting voltage pulses corresponding to a subpart of a vector of input data to the crosspoint array. The voltage pulses generate electric currents that are representative of performing multiplication operations at the crosspoint device based on weight values stored at the crosspoint devices. A set of integrators accumulates an electric charge based on the output electric currents from the respective crosspoint devices. The crosspoint array outputs the accumulated charge after iterating for the predetermined number of times. The accumulated charge represents a multiply-add result of the vector of input data and the one or more convolution kernels.

    Temporal memory adapted for single-shot learning and disambiguation of multiple predictions
    24.
    发明授权
    Temporal memory adapted for single-shot learning and disambiguation of multiple predictions 有权

    公开(公告)号：US11182673B2

    公开(公告)日：2021-11-23

    申请号：US15273141

    申请日：2016-09-22

    申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

    发明人： Geoffrey W. Burr ,  Pritish Narayanan

    IPC分类号： G06N3/08 ,  G06N3/04

    摘要： Single-shot learning and disambiguation of multiple predictions in hierarchical temporal memory is provided. In various embodiments an input sequence is read. The sequence comprises first, second, and third time-ordered components. Each of the time-ordered components is encoded in a sparse distributed representation. The sparse distributed representation of the first time-ordered component is inputted into a first portion of a hierarchical temporal memory. The sparse distributed representation of the second time-ordered component is inputted into a second portion of the hierarchical temporal memory. The second portion is connected to the first portion by a first plurality of synapses. A plurality of predictions as to the third time-ordered component is generated within a third portion of the hierarchical temporal memory. The third portion is connected to the second portion by a second plurality of synapses. Based on the plurality of predictions, additional synaptic connections are added between the first portion and the second portion.

    Controlling aggregate signal amplitude from device arrays by segmentation and time-gating
    25.
    发明授权
    Controlling aggregate signal amplitude from device arrays by segmentation and time-gating 有权

    公开(公告)号：US10453528B1

    公开(公告)日：2019-10-22

    申请号：US16008966

    申请日：2018-06-14

    申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

    发明人： Geoffrey W. Burr ,  Pritish Narayanan

    IPC分类号： G11C11/00 ,  G11C13/00 ,  G06N3/02 ,  G11C11/54

    摘要： High dynamic range resistive arrays are provided. An array of resistive elements provides a vector of current outputs equal to the analog vector-matrix product between (i) a vector of voltage inputs to the array encoding a vector of analog input values and (ii) a matrix of analog resistive weights within the array. First stage current mirrors are electrically coupled to a subset of the resistive elements through a local current accumulation wire. A second stage current mirror is electrically coupled to the first stage current mirrors through a global accumulation wire. Each of the first stage current mirrors includes at least one component having respective scaling factors selectable to scale up or down the current in the local current accumulation wire, thus controlling the aggregate current on the global accumulation wire.

    IMPLICIT VECTOR CONCATENATION WITHIN 2D MESH ROUTING
    28.
    发明申请
    IMPLICIT VECTOR CONCATENATION WITHIN 2D MESH ROUTING 有权

    公开(公告)号：US20230100564A1

    公开(公告)日：2023-03-30

    申请号：US17488827

    申请日：2021-09-29

    申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

    发明人： Geoffrey Burr ,  Kohji Hosokawa ,  HsinYu Tsai ,  Shubham Jain ,  Pritish Narayanan

    IPC分类号： G06N3/063 ,  G06N3/08

    摘要： Arrays of neural cores are provided. Each neural core comprises ordered input wires ordered output wires, and synapses, each of the synapses operatively coupled to one of the input wires and one of the output wires. A plurality of signal wires is provided. At least one of the signal wires is disposed along each dimension of the array of neural cores. A plurality of routers is provided, each of which is operatively coupled to one of the neural cores and to at least one of the signal wires along each of the dimensions of the array of neural cores. Each of the routers selectively routes a signal from the at least one signal wire to its coupled neural core. Each of the routers selectively routes a signal from its coupled neural core to the at least one signal wire. The routers segment the ordered input wires and the ordered output wires into segments and independently routes the signals of each segment.

    System, method and article of manufacture for synchronization-free transmittal of neuron values in a hardware artificial neural networks
    29.
    发明授权
    System, method and article of manufacture for synchronization-free transmittal of neuron values in a hardware artificial neural networks 有权

    公开(公告)号：US11580373B2

    公开(公告)日：2023-02-14

    申请号：US15410769

    申请日：2017-01-20

    申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

    发明人： Geoffrey W Burr ,  Pritish Narayanan

    IPC分类号： G06N3/063 ,  G06N3/04 ,  G06N3/049

    摘要： Computations in Artificial neural networks (ANNs) are accomplished using simple processing units, called neurons, with data embodied by the connections between neurons, called synapses, and by the strength of these connections, the synaptic weights. Crossbar arrays may be used to represent one layer of the ANN with Non-Volatile Memory (NVM) elements at each crosspoint, where the conductance of the NVM elements may be used to encode the synaptic weights, and a highly parallel current summation on the array achieves a weighted sum operation that is representative of the values of the output neurons. A method is outlined to transfer such neuron values from the outputs of one array to the inputs of a second array with no need for global clock synchronization, irrespective of the distances between the arrays, and to use such values at the next array, and/or to convert such values into digital bits at the next array.