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    UNCLONABLE ID BASED CHIP-TO-CHIP COMMUNICATION
    22.
    发明申请
    UNCLONABLE ID BASED CHIP-TO-CHIP COMMUNICATION 有权
    基于无符号ID的芯片间通信

    公开(公告)号：US20150163211A1

    公开(公告)日：2015-06-11

    申请号：US14102607

    申请日：2013-12-11

    Applicant: International Business Machines Corporation

    Inventor： Srivatsan Chellappa ,  Toshiaki Kirihata ,  Sami Rosenblatt

    IPC: H04L29/06

    CPC classification number: H04L63/08 ,  G06F21/31 ,  H04L9/3278 ,  H04L63/0876

    Abstract: A first copy of an intrinsic ID of a first node may be stored on a second node. The first node may receive a challenge that causes it to generate a second copy of its intrinsic ID. The second copy and a random value may be used as inputs of a function to generate a first code. The first code is transmitted to the second node. The second node decodes the first code using its local copies of the random value and/or the intrinsic ID. The second node checks the decoded information against its local information and authenticates the first node if there is a match.

    Abstract translation: 可以将第一节点的内部ID的第一副本存储在第二节点上。 第一个节点可能会接收一个挑战，导致它产生其内在ID的第二个副本。 第二副本和随机值可以用作函数的输入以产生第一代码。 第一个代码被传送到第二个节点。 第二个节点使用其随机值和/或固有ID的本地副本解码第一个代码。 第二节点根据其本地信息检查解码的信息，并且如果存在匹配则认证第一节点。

    TSV Structure With A Built-In U-Shaped FET Transistor For Improved Characterization
    23.
    发明申请
    TSV Structure With A Built-In U-Shaped FET Transistor For Improved Characterization 有权
    具有内置U形FET晶体管的TSV结构，用于改进表征

    公开(公告)号：US20140319600A1

    公开(公告)日：2014-10-30

    申请号：US13870038

    申请日：2013-04-25

    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

    Inventor： Chandrasekharan Kothandaraman ,  Sami Rosenblatt ,  Geng Wang

    IPC: H01L29/66 ,  H01L29/78

    CPC classification number: H01L29/66621 ,  H01L21/823437 ,  H01L29/4236 ,  H01L29/4238 ,  H01L29/66787 ,  H01L29/78

    Abstract: A through-the silicon via (TSV) structure providing a built-in TSV U-shaped FET that includes an annular gate shaped as a TSV partially embedded in a substrate, the annular gate having an inner and an outer surface bound by an oxide layer; a drain formed on an isolated epitaxial layer on top of the substrate conformally connecting the gate oxide layer surrounding the inner annular surface of the TSV; a source partially contacting said gate oxide layer conformally contacting gate oxide layer surrounding the outer surface of the TSV.

    Abstract translation: 一种通过硅通孔（TSV）结构提供内置的TSV U形FET，其包括形成为部分地嵌入在衬底中的TSV的环形栅极，所述环形栅极具有由氧化层界定的内表面和外表面 ; 形成在衬底上的隔离外延层上的漏极，共形地连接围绕TSV的内环形表面的栅氧化层; 源极部分地接触所述栅极氧化物层，所述栅极氧化物层保形地接触围绕TSV的外表面的栅极氧化物层。

    PROTOCOL FOR T1 ESTIMATOR FOR QUBITS
    24.
    发明公开
    PROTOCOL FOR T1 ESTIMATOR FOR QUBITS 审中-公开

    公开(公告)号：US20240185106A1

    公开(公告)日：2024-06-06

    申请号：US17936262

    申请日：2022-09-28

    Applicant: International Business Machines Corporation

    Inventor： Malcolm Scott Carroll ,  Sami Rosenblatt ,  Abhinav Kandala

    IPC: G06N10/20

    CPC classification number: G06N10/20

    Abstract: One or more systems, devices, computer program products and/or computer-implemented methods of use provided herein relate to determining estimated energy relaxation times of qubits. A system can comprise a memory configured to store computer executable components; and a processor configured to execute the computer executable components stored in the memory, wherein the computer executable components comprise a sampling component configured to sample a plurality of measurements of an energy relaxation time of a qubit at individual shifted qubit frequencies of a plurality of shifted qubit frequencies of the qubit; and an analysis component configured to perform an analysis, based on a protocol, to determine a correlation frequency-length between individual energy relaxation times measured at the individual shifted qubit frequencies.

    Antenna-based qubit annealing method
    26.
    发明授权
    Antenna-based qubit annealing method 有权

    公开(公告)号：US11812671B2

    公开(公告)日：2023-11-07

    申请号：US17068324

    申请日：2020-10-12

    Applicant: International Business Machines Corporation

    Inventor： Sami Rosenblatt ,  Rasit Onur Topaloglu

    IPC: H01L39/24 ,  H01L39/02 ,  H10N60/01 ,  G06N10/00 ,  H10N60/12 ,  H10N60/80 ,  H10N69/00

    CPC classification number: H10N60/0884 ,  G06N10/00 ,  H10N60/0912 ,  H10N60/12 ,  H10N60/805 ,  H10N69/00

    Abstract: Systems and techniques facilitating antenna-based thermal annealing of qubits are provided. In one example, a radio frequency emitter, transmitter, and/or antenna can be positioned above a superconducting qubit chip having a Josephson junction coupled to a set of one or more capacitor pads. The radio frequency emitter, transmitter, and/or antenna can emit an electromagnetic signal onto the set of one or more capacitor pads. The capacitor pads can function as receiving antennas and therefore receive the electromagnetic signal. Upon receipt of the electromagnetic signal, an alternating current and/or voltage can be induced in the capacitor pads, which current and/or voltage thereby heat the pads and the Josephson junction. The heating of the Josephson junction can change its physical properties, thereby annealing the Josephson junction. In another example, the emitter can direct the electromagnetic signal to avoid unwanted annealing of neighboring qubits on the superconducting qubit chip.

    Shadow mask area correction for tunnel junctions
    28.
    发明授权
    Shadow mask area correction for tunnel junctions 有权

    公开(公告)号：US10976671B2

    公开(公告)日：2021-04-13

    申请号：US16581804

    申请日：2019-09-25

    Applicant: International Business Machines Corporation

    Inventor： Markus Brink ,  Sami Rosenblatt ,  Bryan D. Trimm

    IPC: G03F7/20 ,  G03F1/36 ,  H01L43/12 ,  H01L39/24

    Abstract: A technique relates to correcting an area of overlap between two films created by sequential shadow mask evaporations. At least one process is performed of: correcting design features in an original layout to generate a corrected layout using a software tool, such that the corrected layout modifies shapes of the design features and correcting the design features in the original layout to generate the corrected layout using a lithographic tool, such that the corrected layout modifies the shapes of the design features. The modified shapes of the design features are patterned at locations on a wafer according to the corrected layout using the lithographic tool. A first film is deposited by an initial shadow mask evaporation and a second film by a subsequent shadow mask evaporation to produce corrected junctions at the locations on the wafer, such that the first film and the second film have an overlap.

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