公开(公告)号：US10658493B2

公开(公告)日：2020-05-19

申请号：US16515759

申请日：2019-07-18

Applicant: International Business Machines Corporation

Inventor： Zhenxing Bi ,  Kangguo Cheng ,  Nicolas J. Loubet ,  Xin Miao ,  Wenyu Xu ,  Chen Zhang

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/06

Abstract: Embodiments of the invention are directed to a nano sheet field effect transistor (FET) device that includes a gate spacer and an inner spacer. The gate spacer includes an upper segment and a lower segment. The inner spacer has a first selectivity to etch compositions used in predetermined fabrication operations for forming the inner spacer. The lower segment has the first selectivity to etch compositions used in predetermined fabrication operations for forming the inner spacer. The upper segment has a second selectivity to etch compositions used in predetermined fabrication operations for forming the inner spacer. The first etch selectivity is greater than the second etch selectivity.

公开(公告)号：US20200118886A1

公开(公告)日：2020-04-16

申请号：US16160346

申请日：2018-10-15

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Xin Miao ,  Choonghyun Lee ,  Shogo Mochizuki ,  Hemanth Jagannathan

IPC: H01L21/8238 ,  H01L27/12 ,  H01L21/822 ,  H01L21/8234

Abstract: Semiconductor devices and methods of forming the same include forming a dummy gate over a fin, which has a lower semiconductor layer, an insulating intermediate layer, and an upper semiconductor layer, to establish a channel region and source/drain regions. Source/drain extensions are grown on the lower semiconductor layer. Source/drain extensions are grown on the upper semiconductor layer. The dummy gate is replaced with a gate stack.

公开(公告)号：US20200083106A1

公开(公告)日：2020-03-12

申请号：US16682687

申请日：2019-11-13

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Kangguo Cheng ,  Xin Miao ,  Wenyu Xu ,  Chen Zhang

IPC: H01L21/8234 ,  H01L29/06 ,  H01L23/532 ,  H01L23/528 ,  H01L21/02 ,  H01L27/088 ,  H01L21/768 ,  H01L23/485 ,  H01L29/66 ,  H01L29/78

Abstract: A method of forming a vertical fin field effect transistor (vertical finFET) with a self-aligned bottom source/drain, including forming a doped layer on a substrate, forming one or more vertical fins on the doped layer, forming a protective layer on the one or more vertical fins, wherein the protective layer has a thickness, and forming at least one isolation trench by removing at least a portion of the protective layer on the doped layer, wherein the isolation trench is laterally offset from at least one of the one or more vertical fins by the thickness of the protective layer.

公开(公告)号：US20200075721A1

公开(公告)日：2020-03-05

申请号：US16677723

申请日：2019-11-08

Applicant: International Business Machines Corporation

Inventor： Juntao Li ,  Kangguo Cheng ,  Chen Zhang ,  Xin Miao

IPC: H01L29/06 ,  H01L29/66 ,  H01L29/161 ,  H01L29/40 ,  H01L29/775 ,  B82Y10/00 ,  H01L29/78 ,  H01L29/423

Abstract: A technique relates to a semiconductor device. A stack includes two or more nanowires separated by a high-k dielectric material, the high-k dielectric material being formed on at least a center portion of the two or more nanowires in the stack. A separation space between the two or more nanowires is less than two times a thickness of the high-k dielectric material formed on a side wall of the two or more nanowires. A source or a drain formed on sides of the stack.

公开(公告)号：US20200075720A1

公开(公告)日：2020-03-05

申请号：US16662332

申请日：2019-10-24

Applicant: International Business Machines Corporation

Inventor： Kangguo Cheng ,  Chen Zhang ,  Wenyu Xu ,  Xin Miao

IPC: H01L29/06 ,  H01L21/28 ,  H01L29/66 ,  H01L29/51 ,  H01L29/41 ,  H01L21/02

Abstract: Methods are provided to construct field-effect transistors comprising low-resistance metallic gate structures. A field-effect transistor includes a nanosheet stack and a metal gate which covers a gate region of the nanosheet stack. The nanosheet stack includes nanosheet channel layers and an etch stop layer disposed above an upper nanosheet channel layer. The metal gate includes a work function metal which encapsulates the nanosheet channel layers, and a gate electrode disposed above and in contact with the work function metal. An upper surface of the work function metal is recessed to be substantially coplanar with the etch stop layer. The gate electrode has a resistivity which is less than a resistivity of the work function metal. The etch stop layer protects the portion of the work function metal disposed between the etch stop layer and the upper nanosheet channel layer from being etched when recessing the work function metal.

公开(公告)号：US10580854B2

公开(公告)日：2020-03-03

申请号：US15787065

申请日：2017-10-18

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Kangguo Cheng ,  Sanjay C. Mehta ,  Xin Miao ,  Chun-Chen Yeh

IPC: H01L21/02 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/324 ,  H01L29/66 ,  H01L29/06 ,  H01L29/78 ,  H01L29/08 ,  H01L29/10 ,  H01L29/49

Abstract: A method of forming a punch through stop region in a fin structure is disclosed. The method may include forming a doped glass layer on a fin structure and forming a masking layer on the doped glass layer. The method may further include removing a portion of the masking layer from an active portion of the fin structure, and removing an exposed portion the doped glass layer that is present on the active portion of the fin structure. A remaining portion of the doped glass layer is present on the isolation portion of the fin structure. Dopant from the doped glass layer may then be diffused into the isolation portion of the fin structure to form the punch through stop region between the active portion of the fin structure and a supporting substrate.

公开(公告)号：US20200052095A1

公开(公告)日：2020-02-13

申请号：US16653522

申请日：2019-10-15

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Xin Miao ,  Chen Zhang ,  Kangguo Cheng ,  Wenyu Xu

IPC: H01L29/66 ,  H01L21/225 ,  H01L21/324 ,  H01L29/10 ,  H01L29/78

Abstract: A method of controlling an effective gate length in a vertical field effect transistor is provided. The method includes forming a vertical fin on a substrate, and forming a bottom spacer layer on the substrate adjacent to the vertical fin. The method further includes forming a dummy gate block adjacent to the vertical fin on the bottom spacer layer. The method further includes forming a top spacer adjacent to the vertical fin on the dummy gate block, and removing the dummy gate block to expose a portion of the vertical fin between the top spacer and bottom spacer layer. The method further includes forming an absorption layer on the exposed portion of the vertical fin. The method further includes heat treating the absorption layer and vertical fin to form a dopant modified absorption layer, and removing the dopant modified absorption layer.

公开(公告)号：US10559502B2

公开(公告)日：2020-02-11

申请号：US15488089

申请日：2017-04-14

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Kangguo Cheng ,  Xin Miao ,  Wenyu Xu ,  Chen Zhang

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/08 ,  H01L27/088 ,  H01L27/12 ,  H01L29/417 ,  H01L21/8238 ,  H01L21/8234 ,  H01L21/762

Abstract: A method of fabricating a vertical fin field effect transistor with a merged top source/drain, including, forming a source/drain layer at the surface of a substrate, forming a plurality of vertical fins on the source/drain layer; forming protective spacers on each of the plurality of vertical fins, forming a sacrificial plug between two protective spacers, forming a filler layer on the protective spacers not in contact with the sacrificial plug, and selectively removing the sacrificial plug to form an isolation region trench between the two protective spacers.

公开(公告)号：US20200044056A1

公开(公告)日：2020-02-06

申请号：US16653589

申请日：2019-10-15

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Xin Miao ,  Chen Zhang ,  Kangguo Cheng ,  Wenyu Xu

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/10 ,  H01L21/225 ,  H01L21/324

Abstract: A method of controlling an effective gate length in a vertical field effect transistor is provided. The method includes forming a vertical fin on a substrate, and forming a bottom spacer layer on the substrate adjacent to the vertical fin. The method further includes forming a dummy gate block adjacent to the vertical fin on the bottom spacer layer. The method further includes forming a top spacer adjacent to the vertical fin on the dummy gate block, and removing the dummy gate block to expose a portion of the vertical fin between the top spacer and bottom spacer layer. The method further includes forming an absorption layer on the exposed portion of the vertical fin. The method further includes heat treating the absorption layer and vertical fin to form a dopant modified absorption layer, and removing the dopant modified absorption layer.

公开(公告)号：US20200043915A1

公开(公告)日：2020-02-06

申请号：US16584803

申请日：2019-09-26

Applicant: International Business Machines Corporation

Inventor： Xin Miao ,  Chen Zhang ,  Kangguo Cheng ,  Juntao Li

IPC: H01L27/088 ,  H01L21/8234 ,  H01L23/522 ,  H01L29/78 ,  H01L29/66 ,  H01L29/08 ,  H01L29/786

Abstract: Techniques for forming VFETs with differing gate lengths are provided. In one aspect, a method for forming a VFET device includes: patterning fins in a substrate, wherein at least one of the fins includes a vertical fin channel of a FET1 and at least another one of the fins includes a vertical fin channel of a FET2; forming a bottom source and drain; forming bottom spacers on the bottom source and drain; forming gates surrounding the vertical fin channel of the FET1 and FET2; forming top spacers on the gate; and forming top source and drains at the tops of the fins by varying a positioning of the top source and drains relative to at least one of the vertical fin channel of the FET1 and the FET2 such that the FET1/FET2 have an effective gate length Lgate1/Lgate2, wherein Lgate1>Lgate2. A VFET device is also provided.