公开(公告)号：US11973125B2

公开(公告)日：2024-04-30

申请号：US17586396

申请日：2022-01-27

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Ruilong Xie ,  Hemanth Jagannathan ,  Jay William Strane ,  Eric Miller

IPC: H01L29/66 ,  H01L21/8234 ,  H01L29/78

CPC classification number: H01L29/6656 ,  H01L21/823431 ,  H01L21/823468 ,  H01L29/785

Abstract: Semiconductor devices and methods of forming the same include forming a bottom source/drain structure around a fin. A multi-layer bottom spacer is formed on the bottom source/drain structure, around the fin. Each layer of the multi-layer bottom spacer has a respective vertical height above the bottom source/drain structure, with a layer of the multi-layer bottom spacer that is farthest from the fin having a greater vertical height than a layer that is closest to the fin, to address parasitic capacitance from the bottom source/drain structure.

公开(公告)号：US20240021609A1

公开(公告)日：2024-01-18

申请号：US17812744

申请日：2022-07-15

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Ruilong Xie ,  Hemanth Jagannathan ,  Kangguo Cheng ,  Juntao Li

IPC: H01L27/088 ,  H01L29/417 ,  H01L29/78 ,  H01L29/66 ,  H01L21/8234

CPC classification number: H01L27/088 ,  H01L29/41741 ,  H01L29/7827 ,  H01L29/66666 ,  H01L21/823418 ,  H01L21/823475 ,  H01L21/823481 ,  H01L21/823487

Abstract: Embodiments of present invention provide a transistor structure. The transistor structure includes a first vertical fin of a first vertical transistor, the first vertical fin having a first and a second sidewall and a first and a second vertical end; a first bottom source/drain (S/D) region underneath the first vertical fin, wherein the first bottom S/D region having an edge that vertically aligns with the first vertical end of the first vertical fin; and a first gate stack surrounding the first vertical fin, wherein the first bottom S/D region horizontally extends beyond the first vertical fin, except at the edge of the first bottom S/D region that vertically aligns with the first vertical end of the first vertical fin, to have at least a portion vertically underneath the first gate stack. A method of manufacturing the transistor structure is also provided.

公开(公告)号：US20240014208A1

公开(公告)日：2024-01-11

申请号：US17810652

申请日：2022-07-05

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Ruilong Xie ,  Hemanth Jagannathan ,  Jay William Strane ,  Kangguo Cheng

IPC: H01L27/088 ,  H01L29/06 ,  H01L29/423 ,  H01L21/8234 ,  H01L29/66

CPC classification number: H01L27/088 ,  H01L29/0653 ,  H01L29/42372 ,  H01L21/823487 ,  H01L21/823481 ,  H01L29/66553 ,  H01L29/6653 ,  H01L29/66666 ,  H01L29/7827

Abstract: Embodiments of present invention provide a method of forming a transistor structure. The method includes forming a set of vertical fins on top of a substrate; forming a conformal spacer lining the set of vertical fins and the substrate; forming sidewall spacers next to vertical portions of the conformal spacer; removing portions of the conformal spacer on top of the substrate and between the sidewall spacers; indenting the conformal spacer vertically between the sidewall spacers and the substrate to create openings; forming bottom spacers in the openings; and forming a shallow-trench-isolation (STI) structure between the bottom spacers. A structure formed thereby is also provided.

公开(公告)号：US11842998B2

公开(公告)日：2023-12-12

申请号：US16731210

申请日：2019-12-31

Applicant: International Business Machines Corporation

Inventor： Robin Hsin Kuo Chao ,  Hemanth Jagannathan ,  Choonghyun Lee ,  Chun Wing Yeung ,  Jingyun Zhang

IPC: H01L27/092 ,  H01L29/165 ,  H01L29/161 ,  H01L21/8238 ,  H01L21/02 ,  H01L21/324 ,  H01L29/10 ,  H01L29/78 ,  H01L29/66

CPC classification number: H01L27/0924 ,  H01L21/02532 ,  H01L21/324 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823885 ,  H01L29/1054 ,  H01L29/161 ,  H01L29/165 ,  H01L29/66666 ,  H01L29/7827 ,  H01L29/785

Abstract: A semiconductor device includes a first diffusion region having a first conductivity type, a first SiGe fin formed on the first diffusion region, a second diffusion region having a second conductivity type, and a second SiGe fin formed on the second diffusion region and including a central portion including a first amount of Ge, and a surface portion including a second amount of Ge which is greater than the first amount. A total width of the central portion and the surface portion is substantially equal to a width of the second diffusion region.

公开(公告)号：US20230154801A1

公开(公告)日：2023-05-18

申请号：US18093932

申请日：2023-01-06

Applicant: International Business Machines Corporation

Inventor： Heng Wu ,  Ruilong Xie ,  Su Chen Fan ,  Jay William Strane ,  Hemanth Jagannathan

IPC: H01L21/8238 ,  H01L29/78 ,  H01L29/06 ,  H01L27/092 ,  H01L21/265 ,  H01L29/66

CPC classification number: H01L21/823814 ,  H01L29/7827 ,  H01L29/0653 ,  H01L27/092 ,  H01L21/265 ,  H01L21/823885 ,  H01L29/6656

Abstract: A method includes forming a p-type field effect transistor region and an n-type field effect transistor region into a semiconductor substrate. The method implements a process flow to fabricate highly doped top source/drains with minimal lithography and etching processes. The method permits the formation of VFETs with increased functionality and reduced scaling.

公开(公告)号：US11615990B2

公开(公告)日：2023-03-28

申请号：US16828619

申请日：2020-03-24

Applicant: International Business Machines Corporation

Inventor： Heng Wu ,  Ruilong Xie ,  Su Chen Fan ,  Jay William Strane ,  Hemanth Jagannathan

IPC: H01L21/8238 ,  H01L27/092 ,  H01L29/78 ,  H01L29/06 ,  H01L21/265 ,  H01L29/66

Abstract: A method includes forming a p-type field effect transistor region and an n-type field effect transistor region into a semiconductor substrate. The method implements a process flow to fabricate highly doped top source/drains with minimal lithography and etching processes. The method permits the formation of VFETs with increased functionality and reduced scaling.

公开(公告)号：US20230063973A1

公开(公告)日：2023-03-02

申请号：US17446626

申请日：2021-09-01

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Ruilong Xie ,  Chen Zhang ,  Brent Anderson ,  Robert Robison ,  Ardasheir Rahman ,  Hemanth Jagannathan

IPC: H01L27/06 ,  H01L29/78 ,  H01L21/8234

Abstract: An apparatus comprising a plurality of FET columns located on a substrate. A source/drain layer located around the base of the plurality of FET columns. A dielectric layer located around the source/drain layer, wherein a portion of the dielectric layer that is sandwiched between a first portion of the source/drain layer and a second portion of the source/drain layer. A gate layer, wherein the gate layer has a first portion located on top of the source/drain layer, and wherein the gate layer has a second portion located on top of the portion of the dielectric layer that is sandwiched between a first portion of the source/drain layer and a second portion of the source/drain layer.

公开(公告)号：US11322588B2

公开(公告)日：2022-05-03

申请号：US16601535

申请日：2019-10-14

Applicant: International Business Machines Corporation

Inventor： Fee Li Lie ,  Choonghyun Lee ,  Kangguo Cheng ,  Hemanth Jagannathan ,  Oleg Gluschenkov

IPC: H01L29/08 ,  H01L27/092 ,  H01L29/06 ,  H01L29/66 ,  H01L29/78 ,  H01L21/02 ,  H01L21/8238

Abstract: A nonplanar MOSFET device such as a FinFET or a sacked nanosheets/nanowires FET has a substrate, one or more nonplanar channels disposed on the substrate, and a gate stack enclosing the nonplanar channels. A first source/drain (S/D) region is disposed on the substrate on a source side of the nonplanar channel and second S/D region is disposed on the substrate on a drain side of the nonplanar channel. The first and second S/D regions made of silicon-germanium (SiGe). In some embodiments, both S/D regions are p-type doped. Contact trenches provide a metallic electrical connection to the first and the second source/drain (S/D) regions. The S/D regions have two parts, a first part with a first concentration of germanium (Ge) and a second part with a second, higher Ge concentration that is a surface layer having convex shape and aligned with one of the contact trenches.

公开(公告)号：US11257721B2

公开(公告)日：2022-02-22

申请号：US16813196

申请日：2020-03-09

Applicant: International Business Machines Corporation

Inventor： Ruqiang Bao ,  Hemanth Jagannathan ,  Brent A. Anderson ,  ChoongHyun Lee

IPC: H01L29/78 ,  H01L29/66 ,  H01L27/092 ,  H01L29/08 ,  H01L29/49 ,  H01L21/8238 ,  H01L21/28 ,  H01L23/535

Abstract: A method of forming a semiconductor structure includes forming a plurality of fins over a top surface of a bottom source/drain region disposed over a top surface of a substrate, the fins providing vertical transport channels for a plurality of vertical transport field-effect transistors. The method also includes forming a first gate conductor surrounding a first one of an adjacent pair of the plurality of fins providing a first vertical transport channel for a first vertical transport field-effect transistor, forming a second gate conductor surrounding a second one of the adjacent pair of the plurality of fins providing a second vertical transport channel for a second vertical transport field-effect transistor, and forming at least one shared gate contact to the first gate conductor and the second gate conductor, the at least one shared gate contact being formed at first ends of the adjacent pair of the plurality of fins.

公开(公告)号：US11217692B2

公开(公告)日：2022-01-04

申请号：US16738152

申请日：2020-01-09

Applicant: International Business Machines Corporation

Inventor： Christopher J. Waskiewicz ,  Ruilong Xie ,  Jay William Strane ,  Hemanth Jagannathan

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/66 ,  H01L29/417

Abstract: A semiconductor device includes a substrate, at least one semiconductor vertical fin extending from the substrate, a bottom source/drain region disposed beneath the at least one semiconductor vertical fin, and first and second isolation regions on respective longitudinal sides of the semiconductor vertical fin. Each of the first and second isolation regions extend vertically above the bottom source/drain region. A bottom spacer is disposed on the first and second isolation regions. A spacer segment of the bottom spacer is disposed on a first upper surface portion of the bottom source/drain region adjacent the first isolation region. A dielectric liner underlies at least portions of the first and second isolation regions. A dielectric segment of the dielectric liner is disposed on a second upper surface portion of the bottom source/drain region adjacent the second isolation region. At least one functional gate structure is disposed on the semiconductor vertical fin.