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    Nanosheet device with tri-layer bottom dielectric isolation
    1.
    发明授权
    Nanosheet device with tri-layer bottom dielectric isolation 有权

    公开(公告)号：US12230676B2

    公开(公告)日：2025-02-18

    申请号：US17449060

    申请日：2021-09-27

    Applicant: International Business Machines Corporation

    Inventor： Xin Miao ,  Jingyun Zhang ,  Alexander Reznicek ,  Choonghyun Lee

    IPC: H01L29/10 ,  H01L29/06 ,  H01L29/66 ,  H01L29/78

    Abstract: A nanosheet device includes a bottom dielectric isolation formed by a first portion of a high-k dielectric layer above a semiconductor substrate, a spacer material above the first portion of the high-k dielectric layer and a second portion of the high-k dielectric layer above the spacer material. A sequence of semiconductor channel layers are stacked perpendicularly to the semiconductor substrate above the bottom dielectric isolation and are separated by and vertically aligned with a metal gate stack. Source/drain regions extend laterally from opposite ends of the semiconductor channel layers with a bottom surface of the source/drain regions being in direct contact with the bottom dielectric isolation for electrically isolating the source/drain regions from the semiconductor substrate.

    Contact source/drain resistance
    6.
    发明授权
    Contact source/drain resistance 有权

    公开(公告)号：US11322588B2

    公开(公告)日：2022-05-03

    申请号：US16601535

    申请日：2019-10-14

    Applicant: International Business Machines Corporation

    Inventor： Fee Li Lie ,  Choonghyun Lee ,  Kangguo Cheng ,  Hemanth Jagannathan ,  Oleg Gluschenkov

    IPC: H01L29/08 ,  H01L27/092 ,  H01L29/06 ,  H01L29/66 ,  H01L29/78 ,  H01L21/02 ,  H01L21/8238

    Abstract: A nonplanar MOSFET device such as a FinFET or a sacked nanosheets/nanowires FET has a substrate, one or more nonplanar channels disposed on the substrate, and a gate stack enclosing the nonplanar channels. A first source/drain (S/D) region is disposed on the substrate on a source side of the nonplanar channel and second S/D region is disposed on the substrate on a drain side of the nonplanar channel. The first and second S/D regions made of silicon-germanium (SiGe). In some embodiments, both S/D regions are p-type doped. Contact trenches provide a metallic electrical connection to the first and the second source/drain (S/D) regions. The S/D regions have two parts, a first part with a first concentration of germanium (Ge) and a second part with a second, higher Ge concentration that is a surface layer having convex shape and aligned with one of the contact trenches.

    Oxygen vacancy passivation in high-k dielectrics for vertical transport field effect transistor
    9.
    发明授权
    Oxygen vacancy passivation in high-k dielectrics for vertical transport field effect transistor 有权

    公开(公告)号：US11251094B2

    公开(公告)日：2022-02-15

    申请号：US16784365

    申请日：2020-02-07

    Applicant: International Business Machines Corporation

    Inventor： Choonghyun Lee ,  Takashi Ando ,  Alexander Reznicek ,  Jingyun Zhang

    IPC: H01L21/8238 ,  H01L27/092

    Abstract: Embodiments of the present invention are directed to fabrication method and resulting structures for vertical tunneling field effect transistors (VFETs) having an oxygen vacancy passivating bottom spacer. In a non-limiting embodiment of the invention, a first semiconductor fin is formed in a first region of a substrate and a second semiconductor fin is formed in a second region of the substrate. A bilayer bottom spacer is formed in direct contact with sidewalls of the semiconductor fins. The bilayer bottom spacer includes a first layer and an oxygen-donating second layer positioned on the first layer. A first dielectric film is formed on the sidewalls of the first semiconductor fin. The first dielectric film terminates on the first layer. A second dielectric film is formed on the sidewalls of the second semiconductor fin. The second dielectric film extends onto a surface of the oxygen-donating second layer.

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