公开(公告)号：US09831115B2

公开(公告)日：2017-11-28

申请号：US15435428

申请日：2017-02-17

申请人： SunEdison Semiconductor Limited (UEN201334164H)

发明人： Igor Peidous ,  Andrew M. Jones ,  Srikanth Kommu ,  Jeffrey L. Libbert

IPC分类号： H01L21/762 ,  H01L21/324 ,  H01L29/04 ,  H01L29/40 ,  H01L29/30 ,  H01L21/28 ,  H01L21/18 ,  H01L21/265

CPC分类号： H01L21/76251 ,  H01L21/187 ,  H01L21/26506 ,  H01L21/28282 ,  H01L21/76254 ,  H01L29/045 ,  H01L29/30 ,  H01L29/408

摘要： A cost effective process flow for manufacturing semiconductor on insulator structures is parallel is provided. Each of the multiple semiconductor-on-insulator composite structures prepared in parallel comprises a charge trapping layer (CTL).

公开(公告)号：US20170338143A1

公开(公告)日：2017-11-23

申请号：US15526798

申请日：2015-11-13

申请人： SUNEDISON SEMICONDUCTOR LIMITED

发明人： Igor Peidous ,  Jeffrey L. Libbert ,  Srikanth Kommu ,  Andrew M. Jones ,  Samuel Christopher Pratt ,  Horacio Josue Mendez ,  Leslie George Stanton ,  Michelle Rene Dickinson

IPC分类号： H01L21/762 ,  H01L21/02

CPC分类号： H01L21/76251 ,  H01L21/02164 ,  H01L21/02238 ,  H01L21/02255 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/02595 ,  H01L21/0262 ,  H01L21/76254

摘要： A method of preparing a single crystal semiconductor handle wafer in the manufacture of a semiconductor-on-insulator device is provided. The single crystal semiconductor handle wafer is prepared to comprise a charge trapping layer, which is oxidized. The buried oxide layer in the resulting semiconductor-on-insulator device comprises an oxidized portion of the charge trapping layer and an oxidized portion of the single crystal semiconductor device layer.

公开(公告)号：US10483152B2

公开(公告)日：2019-11-19

申请号：US15526640

申请日：2015-11-16

申请人： SunEdison Semiconductor Limited (UEN201334164H)

发明人： Igor Peidous ,  Lu Fei ,  Jeffrey L. Libbert ,  Andrew M. Jones ,  Alex Usenko ,  Gang Wang ,  Shawn George Thomas ,  Srikanth Kommu

IPC分类号： H01L21/76 ,  H01L21/762

摘要： A semiconductor on insulator multilayer structure is provided. The multilayer comprises a high resistivity single crystal semiconductor handle substrate, an optionally relaxed semiconductor layer comprising silicon, germanium, or silicon germanium, an optional polycrystalline silicon layer, a dielectric layer, and a single crystal semiconductor device layer.

公开(公告)号：US10283402B2

公开(公告)日：2019-05-07

申请号：US15554034

申请日：2016-02-25

申请人： SunEdison Semiconductor Limited (UEN201334164H)

发明人： Gang Wang ,  Jeffrey L. Libbert ,  Shawn George Thomas ,  Igor Peidous

IPC分类号： H01L21/762 ,  H01L21/763 ,  H01L27/12 ,  H01L21/02

摘要： A semiconductor on insulator multilayer structure is provided. The multilayer comprises a high resistivity single crystal semiconductor handle substrate, a textured oxide, nitride, or oxynitride layer, a polycrystalline silicon layer, a dielectric layer, and a single crystal semiconductor device layer. The multilayer structure is prepared in a manner that reduces wafer bow.

公开(公告)号：US20180174892A1

公开(公告)日：2018-06-21

申请号：US15899636

申请日：2018-02-20

申请人： SunEdison Semiconductor Limited (UEN201334164H)

发明人： Igor Peidous ,  Jeffrey L. Libbert

IPC分类号： H01L21/762 ,  H01L29/06 ,  H01L21/02 ,  H01L21/265 ,  H01L21/761 ,  H01L21/304

CPC分类号： H01L21/76254 ,  H01L21/0214 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02181 ,  H01L21/02186 ,  H01L21/02189 ,  H01L21/02192 ,  H01L21/02238 ,  H01L21/02255 ,  H01L21/02381 ,  H01L21/02488 ,  H01L21/02532 ,  H01L21/02576 ,  H01L21/02595 ,  H01L21/0262 ,  H01L21/02634 ,  H01L21/26513 ,  H01L21/26533 ,  H01L21/304 ,  H01L21/3226 ,  H01L21/761 ,  H01L29/0646 ,  H01L29/0649

摘要： A multilayer composite structure and a method of preparing a multilayer composite structure are provided. The multilayer composite structure comprises a semiconductor handle substrate having a minimum bulk region resistivity of at least about 500 ohm-cm and an isolation region that impedes the transfer of charge carriers along the surface of the handle substrate and reduces parasitic coupling between RF devices.

公开(公告)号：US20170372946A1

公开(公告)日：2017-12-28

申请号：US15623519

申请日：2017-06-15

申请人： SunEdison Semiconductor Limited (UEN201334164H)

发明人： Igor Peidous ,  Jeffrey L. Libbert

IPC分类号： H01L21/762 ,  H01L21/304 ,  H01L21/265 ,  H01L21/761 ,  H01L29/06 ,  H01L21/02

CPC分类号： H01L21/76254 ,  H01L21/0214 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02181 ,  H01L21/02186 ,  H01L21/02189 ,  H01L21/02192 ,  H01L21/02238 ,  H01L21/02255 ,  H01L21/02381 ,  H01L21/02488 ,  H01L21/02532 ,  H01L21/02576 ,  H01L21/02595 ,  H01L21/0262 ,  H01L21/02634 ,  H01L21/26513 ,  H01L21/26533 ,  H01L21/304 ,  H01L21/3226 ,  H01L21/761 ,  H01L29/0646 ,  H01L29/0649

摘要： A multilayer composite structure and a method of preparing a multilayer composite structure are provided. The multilayer composite structure comprises a semiconductor handle substrate having a minimum bulk region resistivity of at least about 500 ohm-cm and an isolation region that impedes the transfer of charge carriers along the surface of the handle substrate and reduces parasitic coupling between RF devices.

公开(公告)号：US20170316968A1

公开(公告)日：2017-11-02

申请号：US15526640

申请日：2015-11-16

申请人： SunEdison Semiconductor Limited (UEN201334164H)

发明人： Igor Peidous ,  Lu Fei ,  Jeffrey L. Libbert ,  Andrew M. Jones ,  Alex Usenko ,  Gang Wang ,  Shawn George Thomas ,  Srikanth Kommu

IPC分类号： H01L21/762

摘要： A semiconductor on insulator multilayer structure is provided. The multilayer comprises a high resistivity single crystal semiconductor handle substrate, an optionally relaxed semiconductor layer comprising silicon, germanium, or silicon germanium, an optional polycrystalline silicon layer, a dielectric layer, and a single crystal semiconductor device layer.

公开(公告)号：US09640666B2

公开(公告)日：2017-05-02

申请号：US11781664

申请日：2007-07-23

申请人： Igor Peidous

发明人： Igor Peidous

IPC分类号： H01L21/70 ,  H01L29/786 ,  H01L21/8238 ,  H01L21/84 ,  H01L27/12 ,  H01L29/06 ,  H01L29/66 ,  H01L29/78

CPC分类号： H01L29/78603 ,  H01L21/823807 ,  H01L21/823878 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/0649 ,  H01L29/66636 ,  H01L29/7848 ,  H01L29/78687 ,  H01L29/78696

摘要： An integrated circuit that includes: providing a substrate including a support structure, a dielectric layer, and a variable thickness film processed to include the dielectric layer within a recess of the variable thickness film; forming a gate over the variable thickness film; and forming a channel and a source/drain within the variable thickness film.

公开(公告)号：US07704840B2

公开(公告)日：2010-04-27

申请号：US11611784

申请日：2006-12-15

申请人： Igor Peidous ,  Rohit Pal

发明人： Igor Peidous ,  Rohit Pal

IPC分类号： H01L21/336

CPC分类号： H01L29/78687 ,  H01L29/66553 ,  H01L29/66621 ,  H01L29/66628 ,  H01L29/66772 ,  H01L29/7848

摘要： A stress enhanced MOS transistor and methods for its fabrication are provided. A semiconductor-on-insulator structure is provided which includes a semiconductor layer having a first surface. A strain-inducing epitaxial layer is blanket deposited over the first surface, and can then be used to create a source region and a drain region which overlie the first surface.

摘要翻译： 提供了一种应力增强型MOS晶体管及其制造方法。 提供了一种绝缘体上半导体结构，其包括具有第一表面的半导体层。 应变诱导外延层被覆盖地沉积在第一表面上，然后可用于产生覆盖在第一表面上的源极区域和漏极区域。

公开(公告)号：US20100078825A1

公开(公告)日：2010-04-01

申请号：US12240061

申请日：2008-09-29

申请人： Ryan James Patz ,  Igor Peidous ,  Jeremiah Pender ,  Michael D. Armacost

发明人： Ryan James Patz ,  Igor Peidous ,  Jeremiah Pender ,  Michael D. Armacost

IPC分类号： H01L23/48 ,  H01L21/4763

CPC分类号： H01L21/76807 ,  H01L21/67253 ,  H01L21/76844 ,  H01L21/76846 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

摘要： Described herein are methods for fabricating dual-damascene interconnect structures. In one embodiment, the interconnect structures are fabricated with a dual-damascene method having trenches then vias formed. The method includes novel liner depositions after the trench and via etches. The method includes etching trenches in a dielectric layer. Next, the method includes depositing a first liner layer on the dielectric layer. Next, the method includes etching vias in the dielectric layer and an etch stop layer. Next, the method includes depositing a second liner layer on the first liner layer. The second liner layer is deposited on the exposed surfaces of the first liner layer, dielectric layer, etch stop layer, and the first metal layer. Then, a second metal layer is deposited on the second liner layer.

摘要翻译： 这里描述了制造双镶嵌互连结构的方法。 在一个实施例中，使用具有沟槽然后形成通孔的双镶嵌法制造互连结构。 该方法包括在沟槽和经过蚀刻之后的新型衬垫沉积。 该方法包括蚀刻电介质层中的沟槽。 接下来，该方法包括在介电层上沉积第一衬里层。 接下来，该方法包括蚀刻介电层中的通孔和蚀刻停止层。 接下来，该方法包括在第一衬里层上沉积第二衬里层。 第二衬里层沉积在第一衬里层，电介质层，蚀刻停止层和第一金属层的暴露表面上。 然后，第二金属层沉积在第二衬垫层上。