公开(公告)号：US20140223569A1

公开(公告)日：2014-08-07

申请号：US14137065

申请日：2013-12-20

Applicant: Infineon Technologies AG

Inventor： Markus Gail ,  Gerd Dirscherl ,  Marcus Janke

IPC: G06F21/60

CPC classification number: G06F21/60 ,  G06F21/00 ,  G06F21/71 ,  G06F2221/2121

Abstract: An embedded security module includes a security processor, volatile and non-volatile memory, and an interface. The security processor includes transistors formed in one or more semiconductor layers of a semiconductor die, and implements one or more security-related functions on data and/or code accessed by the security processor. The volatile memory is fabricated on the same semiconductor die as the security processor and stores the data and/or code accessed by the security processor. The non-volatile memory includes non-volatile storage cells disposed above each semiconductor layer of the semiconductor die, and securely stores at least one of the data and/or code accessed by the security processor and security information relating to the data and/or code accessed by the security processor. The interface is fabricated on the same semiconductor die as the security processor and provides a communication interface for the security processor.

Abstract translation: 嵌入式安全模块包括安全处理器，易失性和非易失性存储器以及接口。 安全处理器包括形成在半导体管芯的一个或多个半导体层中的晶体管，并且对由安全处理器访问的数据和/或代码实现一个或多个与安全相关的功能。 易失性存储器被制造在与安全处理器相同的半导体管芯上，并存储由安全处理器访问的数据和/或代码。 非易失性存储器包括设置在半导体芯片的每个半导体层之上的非易失性存储单元，并且安全地存储由安全处理器访问的数据和/或代码中的至少一个以及与数据和/或代码相关的安全信息 由安全处理器访问。 该接口在与安全处理器相同的半导体管芯上制造，并为安全处理器提供通信接口。

公开(公告)号：US20130176053A1

公开(公告)日：2013-07-11

申请号：US13775789

申请日：2013-02-25

Applicant: INFINEON TECHNOLOGIES AG

Inventor： Berndt Gammel ,  Thomas Nirschl ,  Gerd Dirscherl ,  Philip Schlazer ,  Stefan Rueping

IPC: H03K19/20

CPC classification number: H03K19/20 ,  G11C13/0004 ,  H01L27/24

Abstract: An integrated circuit has one or more logic gates and a control circuit. The control circuit has one or more control elements coupled to the logic gates. The control circuit controls the states of the one or more logic gates.

Abstract translation: 集成电路具有一个或多个逻辑门和控制电路。 控制电路具有耦合到逻辑门的一个或多个控制元件。 控制电路控制一个或多个逻辑门的状态。

公开(公告)号：US20240012903A1

公开(公告)日：2024-01-11

申请号：US18217693

申请日：2023-07-03

Applicant: Infineon Technologies AG

Inventor： Roland Ebrecht ,  Gerd Dirscherl ,  Stefan Hackenberg ,  Florian Mendel ,  Stefan Witossek

IPC: G06F21/51

CPC classification number: G06F21/51

Abstract: A method for executing a program on a data processing device, the method comprising storing multiple program instructions and data to be processed by a processor of the data processing device in one or more memories of the data processing device; receiving, from an external data processing device, a reference value for a check of the multiple program instructions; computing a check value from the multiple program instructions for the check by way of the data processing device when the program instructions are loaded from the one or more memories into an instruction buffer memory of the data processing device or by way of read access to the instruction buffer memory after the program instructions have been loaded into the instruction buffer memory from the one or more memories; and executing at least some of the program instructions if the check value matches the received reference value.

公开(公告)号：US11342939B2

公开(公告)日：2022-05-24

申请号：US16986300

申请日：2020-08-06

Applicant: Infineon Technologies AG

Inventor： Bernd Meyer ,  Gerd Dirscherl

IPC: G11C29/00 ,  H03M13/15 ,  G06F11/10 ,  H03M13/00

Abstract: It is proposed to divide data read from a memory into groups and to perform a syndrome calculation iteratively based on each of the individual groups. The syndromes may be calculated by means of random access to the individual groups.

公开(公告)号：US10475520B2

公开(公告)日：2019-11-12

申请号：US15821871

申请日：2017-11-24

Applicant: Infineon Technologies AG

Inventor： Jan Otterstedt ,  Robin Boch ,  Gerd Dirscherl ,  Bernd Meyer ,  Christian Peters ,  Steffen Sonnekalb

IPC: G11C7/22 ,  G11C29/02 ,  G11C7/06 ,  G11C29/12 ,  G11C29/00 ,  G11C29/44

Abstract: A memory circuit includes electrically programmable memory cells arranged in a non-volatile memory cell array along rows and columns, word lines, each word line coupled with one or more memory cells, non-volatile marking memory cells, wherein at least one word line of the word lines is associated with one or more marking memory cells, and marking bit lines, each associated with marking memory cells, marking source lines, each associated with marking memory cells, wherein, for marking memory cells, a physical connection from an associated marking source line and/or from an associated marking bit line to the marking memory cells defines those marking memory cells to a non-changeable state, wherein the marking memory cells are configured to identify the associated word line of respective marking memory cells in the non-changeable memory state.

公开(公告)号：US10276222B2

公开(公告)日：2019-04-30

申请号：US14710617

申请日：2015-05-13

Applicant: Infineon Technologies AG

Inventor： Thomas Kuenemund ,  Gerd Dirscherl ,  Gunther Fenzl ,  Joel Hatsch ,  Nikolai Sefzik

IPC: G11C7/12 ,  G11C11/419 ,  G11C7/10 ,  G11C8/06 ,  G11C8/18 ,  G11C11/408 ,  G11C11/415

Abstract: In accordance with one embodiment, a method for accessing a memory is provided, including carrying out a first access to the memory and charging, for a memory cell, a bit line coupled to the memory cell to a value which is stored or to be stored in the memory cell, holding the state of the bit line until a second access, which follows the first access, and outputting the held state if the second access is a read access to the memory cell.

公开(公告)号：US10009357B2

公开(公告)日：2018-06-26

申请号：US14728323

申请日：2015-06-02

Applicant: Infineon Technologies AG

Inventor： Albrecht Mayer ,  Gerd Dirscherl ,  Wieland Fischer

IPC: H04L29/06 ,  H04L29/08 ,  H04L12/40 ,  H04L9/32

CPC classification number: H04L63/12 ,  H04L9/3226 ,  H04L12/40 ,  H04L63/04 ,  H04L63/123 ,  H04L63/126 ,  H04L63/1441 ,  H04L67/10 ,  H04L2012/40273 ,  H04L2209/34

Abstract: A method for generating a data frame is disclosed which contains a user data block with the message and a code block. To generate the code block, a first data record is initially coded by means of a first coding algorithm in order to calculate a first code word. Subsequently, the message is transformed. By using the first code words thus generated and the transformed message, a second code word is subsequently calculated by using a second coding algorithm. The data frame comprises the second code word but not the first code word.

公开(公告)号：US20160042160A1

公开(公告)日：2016-02-11

申请号：US14453116

申请日：2014-08-06

Applicant: Infineon Technologies AG

Inventor： Witold Gora ,  Andreas Geiler ,  Gerd Dirscherl ,  Albrecht Mayer

IPC: G06F21/12 ,  G06F21/14

CPC classification number: G06F21/12 ,  G06F21/14 ,  G06F21/602 ,  G06F2221/0744

Abstract: An apparatus and corresponding method for preventing cloning of code. The apparatus includes a memory, an authentication module, and a device. The memory is configured to store the code, which includes unencrypted code and a fragment of encrypted code. The authentication module is configured to receive and decrypt the fragment of encrypted code from the memory into a fragment of decrypted code, and to store the fragment of decrypted code in an authentication module buffer. The device configured to execute the unencrypted code from the memory and to execute the fragment of decrypted code from the authentication module buffer, wherein the fragment of encrypted code is personalized to the device.

Abstract translation: 一种用于防止代码克隆的装置和相应方法。 该装置包括存储器，认证模块和设备。 存储器被配置为存储代码，其包括未加密的代码和加密代码的片段。 认证模块被配置为将加密代码的片段从存储器接收并解密成解密代码的片段，并将解密的代码片段存储在认证模块缓冲器中。 所述设备被配置为从所述存储器执行未加密的代码并且从所述认证模块缓冲器执行解密代码的片段，其中所述加密代码片段被个性化到所述设备。

公开(公告)号：US20150350241A1

公开(公告)日：2015-12-03

申请号：US14728323

申请日：2015-06-02

Applicant: Infineon Technologies AG

Inventor： Albrecht Mayer ,  Gerd Dirscherl ,  Wieland Fischer

IPC: H04L29/06 ,  H04L29/08 ,  H04L12/40

CPC classification number: H04L63/12 ,  H04L9/3226 ,  H04L12/40 ,  H04L63/04 ,  H04L63/123 ,  H04L63/126 ,  H04L63/1441 ,  H04L67/10 ,  H04L2012/40273 ,  H04L2209/34

Abstract: A method for generating a data frame is disclosed which contains a user data block with the message and a code block. To generate the code block, a first data record is initially coded by means of a first coding algorithm in order to calculate a first code word. Subsequently, the message is transformed. By using the first code words thus generated and the transformed message, a second code word is subsequently calculated by using a second coding algorithm. The data frame comprises the second code word but not the first code word.

Abstract translation: 公开了一种用于产生数据帧的方法，其包含具有消息的用户数据块和代码块。 为了生成代码块，首先通过第一编码算法对第一数据记录进行编码，以便计算第一代码字。 随后，消息被转换。 通过使用如此生成的第一码字和变换消息，随后通过使用第二编码算法来计算第二码字。 数据帧包括第二码字而不是第一码字。