公开(公告)号：US20170126261A1

公开(公告)日：2017-05-04

申请号：US14931195

申请日：2015-11-03

Applicant: Infineon Technologies AG

Inventor： Peter Singerl ,  Thomas Magesacher ,  Martin Mataln

IPC: H04B1/04

CPC classification number: H04B1/0475 ,  H03F1/3247 ,  H03F1/3294 ,  H03F2200/102 ,  H04B2001/0425

Abstract: An RF transmitter arrangement using analog pre-distortion is disclosed. The arrangement includes lower bandwidth circuitry, an analog pre-distorter, and a non-linear amplifier chain. The lower bandwidth circuitry is configured to generate an analog signal. The analog pre-distorter is configured to apply a non-linear distortion to the analog original signal based on a coupled feedback signal in order to generate an RF output signal. The non-linear amplifier chain is configured to amplify the RF output signal to generate a transmission signal relative to the analog original signal. The coupled feedback signal is derived from the transmission signal.

公开(公告)号：US20160373072A1

公开(公告)日：2016-12-22

申请号：US15251266

申请日：2016-08-30

Applicant: Infineon Technologies AG

Inventor： Thomas Magesacher ,  Peter Singerl ,  Martin Mataln ,  Christian Schuberth

IPC: H03F1/32 ,  H03F3/189 ,  H03F3/24 ,  H04B1/04

CPC classification number: H03F1/3247 ,  H03F1/3241 ,  H03F1/34 ,  H03F3/189 ,  H03F3/24 ,  H03F2200/451 ,  H04B1/0475 ,  H04B2001/0425 ,  H04B2001/0433

Abstract: A non-linear pre-distortion engine maintaining constant peak power at its output is disclosed. The engine includes a compression estimator, a crest factor reduction processor, a digital pre-distorter and a power amplifier. The compression estimator is configured to generate a compression estimate based on an input signal and a feedback signal. The feedback signal is based on an RF output signal. The crest factor reduction processor is configured to reduce a crest factor of the input signal to generate a crest factor reduced signal based on the compression estimate. The digital pre-distorter is configured to apply a pre-distortion to the crest factor reduced signal after an initial phase and generate a pre-distorted signal based on pre-distortion parameters. The power amplifier is configured to amplify the pre-distorted signal to generate the RF output signal. The operation of the chain consisting of pre-distorter and power amplifier is substantially linear and the pre-distorter maintains constant peak power at its output, which eliminates unwanted avalanche or pre-distorter blow-up issues.

Abstract translation: 公开了在其输出端保持恒定峰值功率的非线性预失真引擎。 引擎包括压缩估计器，波峰因数降低处理器，数字预失真器和功率放大器。 压缩估计器被配置为基于输入信号和反馈信号产生压缩估计。 反馈信号基于RF输出信号。 波峰因数降低处理器被配置为降低输入信号的波峰因数，以基于压缩估计产生波峰因数降低信号。 数字预失真器被配置为在初始相位之后对波峰因数降低信号施加预失真，并且基于预失真参数产生预失真信号。 功率放大器被配置为放大预失真信号以产生RF输出信号。 由预失真器和功率放大器组成的链条的操作基本上是线性的，并且预失真器在其输出端保持恒定的峰值功率，这消除了不必要的雪崩或预失真器爆炸问题。

公开(公告)号：US09099996B2

公开(公告)日：2015-08-04

申请号：US14079923

申请日：2013-11-14

Applicant: Infineon Technologies AG

Inventor： David Seebacher ,  Peter Singerl ,  Christian Schuberth ,  Martin Mataln

IPC: H03K7/08

CPC classification number: H03K7/08

Abstract: A method for providing cross point information includes: providing an input signal having amplitude and phase information; interpolating between a first point of the input signal and a second point of the input signal to provide cross point information between the first point and the second point; and providing a pulse-width modulated signal based on the input signal and the cross point information.

Abstract translation: 提供交叉点信息的方法包括：提供具有振幅和相位信息的输入信号; 在所述输入信号的第一点和所述输入信号的第二点之间进行内插以在所述第一点和所述第二点之间提供交叉点信息; 以及基于输入信号和交叉点信息提供脉冲宽度调制信号。

公开(公告)号：US20230283243A1

公开(公告)日：2023-09-07

申请号：US18172008

申请日：2023-02-21

Applicant: Infineon Technologies AG

Inventor： Herwig Wappis ,  Peter Singerl ,  Martin Mataln ,  Gerhard Maderbacher

IPC: H03F1/30 ,  G05F3/20 ,  H03F1/02

CPC classification number: H03F1/302 ,  G05F3/205 ,  H03F1/0266

Abstract: A circuit for biasing a transistor is provided. The circuit includes an output terminal configured to be coupled to a gate terminal of the transistor and circuitry. In a first state, the circuitry is configured to output a control signal at a first voltage level for setting the transistor to a first transistor state. In a second state, the circuitry is configured to first output the control signal at a second voltage level different from the first voltage level following by changing the control signal from the second voltage level towards a third voltage level different from the first and second voltage level over time.

公开(公告)号：US20200313635A1

公开(公告)日：2020-10-01

申请号：US16903011

申请日：2020-06-16

Applicant: Infineon Technologies AG

Inventor： David Seebacher ,  Pantelis Sarais ,  Peter Singerl ,  Herwig Wappis

IPC: H03F3/24 ,  H03F1/02 ,  H04B1/401 ,  H03F3/193 ,  H03F3/19 ,  H03F3/45 ,  H04B1/38 ,  H04J3/02

Abstract: Devices and methods for generating a bias voltage for a transceiver operating in time division multiplexing operation, and corresponding transceivers are provided. In this case, the bias voltage is controlled in guard intervals between transmission and reception of signals by the transceiver.

公开(公告)号：US10574593B2

公开(公告)日：2020-02-25

申请号：US15491442

申请日：2017-04-19

Applicant: Infineon Technologies AG

Inventor： Pantelis Sarais ,  Peter Singerl

IPC: H04L12/933 ,  H04L12/937 ,  H04W52/02

Abstract: Techniques are provided for sorting input data values using a sorting circuit. The sorting circuit includes a single stage of comparators coupled to a bank of registers. Multiplexors and a sequencer are used to route the comparator outputs back to the comparator inputs such that the comparators may be re-used over multiple sorting phases so as to order an input sequence of data values into a partially-sorted sequence or into a completely-sorted sequence that is monotonically increasing or decreasing. By re-using the comparators, the hardware required for such sorting is significantly reduced relative to conventional techniques. Also described are techniques for median filtering, which use a sorted sequence as output by the sorting circuit described herein.

公开(公告)号：US20190280360A1

公开(公告)日：2019-09-12

申请号：US16277398

申请日：2019-02-15

Applicant: Infineon Technologies AG

Inventor： David Seebacher ,  Andrea Del Chiaro ,  Christian Schuberth ,  Peter Singerl ,  Ji Zhao

IPC: H01P3/08 ,  H01P3/16

Abstract: A device includes at least one electrically conductive structure and at least one stripline. The stripline includes stripline sections that are connected to one another in a series connection between a first terminal and a second terminal. A first subset of the stripline sections is arranged on a first side of the conductive structure and a second subset of the stripline sections is arranged on a second side of the conductive structure. The device also includes at least one conductive connection between the first subset of the stripline sections and the second subset of the stripline sections, wherein the at least one conductive connection is isolated from the at least one electrically conductive structure.

公开(公告)号：US10069662B2

公开(公告)日：2018-09-04

申请号：US14937040

申请日：2015-11-10

Applicant: Infineon Technologies AG

Inventor： Yannis Papananos ,  David Seebacher ,  Nikolaos Alexiou ,  Franz Dielacher ,  Konstantinos Galanopoulos ,  Peter Singerl ,  Marc Tiebout

IPC: H04K1/10 ,  H02M1/14 ,  H04L25/49 ,  H04L27/18

Abstract: A pulse width modulation system comprises an analog component and a digital component. The analog component operates to separate a local oscillator signal with different phase shifts and introduce an offset (i.e., a time delay) to analog signals being receive at an input with a tuning operation that fine tunes in the analog signals in the analog (continuous time) domain. The analog component comprises a plurality of analog delay lines that respectively process carrier signals having a different phase shifts. Digital delay lines convert the analog signals to digital square waves with the same time delay and at the same resolution as the analog output signal.

公开(公告)号：US09520923B2

公开(公告)日：2016-12-13

申请号：US14704294

申请日：2015-05-05

Applicant: Infineon Technologies AG

Inventor： Peter Singerl ,  David Seebacher ,  Thomas Magesacher ,  Franz Dielacher

IPC: H04B7/04 ,  H04B1/04 ,  H04L27/20 ,  H04L25/49

CPC classification number: H04L27/205 ,  H04B1/0475 ,  H04B1/0483 ,  H04L25/4902

Abstract: The present disclosure relates to a low-complexity transmitter architecture that drives phase modulators with digital signals to generate a pulse width modulated (PWM) signal that is transmitted by an antenna. In some embodiments, the system has a pre-processing element that generates first and second digital control signals from a digital baseband signal. A first phase modulation component introduces a first phase shift into a first local oscillator signal based upon the first control signal and generates a first digital signal corresponding to the first phase shift. A second phase modulation component introduces a second phase shift into the first local oscillator signal based upon the second control signal and generates a second digital signal corresponding to the second phase shift. A combination element is configured to combine the first and second digital output signals to generate an RF pulse width modulated (RF-PWM) signal.

Abstract translation: 本公开涉及一种低复杂度的发射机架构，其用数字信号驱动相位调制器以产生由天线发射的脉宽调制（PWM）信号。 在一些实施例中，系统具有从数字基带信号产生第一和第二数字控制信号的预处理元件。 第一相位调制分量基于第一控制信号将第一相移引入第一本地振荡器信号，并产生对应于第一相移的第一数字信号。 第二相位调制分量基于第二控制信号将第二相移引入第一本地振荡器信号，并产生对应于第二相移的第二数字信号。 组合元件被配置为组合第一和第二数字输出信号以产生RF脉冲宽度调制（RF-PWM）信号。

公开(公告)号：US09484962B1

公开(公告)日：2016-11-01

申请号：US14731586

申请日：2015-06-05

Applicant: Infineon Technologies AG

Inventor： Thomas Magesacher ,  Peter Singerl ,  Martin Mataln

IPC: H04L5/00 ,  H04B1/04

CPC classification number: H04B1/0475 ,  H03F1/3241 ,  H04B2001/0425

Abstract: One embodiment relates to a system which includes a pre-distortion unit, a power amplifier circuit, a power amplifier model, and a parameter estimation unit. The pre-distortion unit is configured to pre-distort an input signal based on a model parameter by directly computing the model inverse in an iterative fashion, thereby providing a pre-distorted signal. The power amplifier circuit is configured to amplify the pre-distorted signal. The power amplifier model is configured to model amplification of the pre-distorted signal by the power amplifier circuit based on the pre-distorted signal and the model parameter. Based on the pre-distorted signal and an error signal, the parameter estimation unit is configured to update the model parameter provided to the pre-distortion unit and the power amplifier model. The error signal represents a difference between an output signal from the power amplifier circuit and a modeled output signal from the power amplifier model.

Abstract translation: 一个实施例涉及一种包括预失真单元，功率放大器电路，功率放大器模型和参数估计单元的系统。 预失真单元被配置为通过以迭代方式直接计算模型逆矩阵来基于模型参数来预失真输入信号，从而提供预失真信号。 功率放大器电路被配置为放大预失真信号。 功率放大器模型被配置为基于预失真信号和模型参数来由功率放大器电路建模预失真信号的放大。 基于预失真信号和误差信号，参数估计单元被配置为更新提供给预失真单元和功率放大器模型的模型参数。 误差信号表示来自功率放大器电路的输出信号与来自功率放大器模型的建模输出信号之间的差异。