公开(公告)号：US11152396B2

公开(公告)日：2021-10-19

申请号：US16651030

申请日：2017-12-26

申请人： Intel Corporation

发明人： Aaron D. Lilak ,  Rishabh Mehandru ,  Gilbert Dewey ,  Willy Rachmady

IPC分类号： H01L27/12 ,  H01L21/768 ,  H01L21/84 ,  H01L23/522 ,  H01L23/528 ,  H01L25/065 ,  H01L29/78 ,  H01L21/8234 ,  H01L29/786 ,  H01L27/088 ,  H01L21/822 ,  H01L27/06 ,  H01L29/04 ,  H01L29/24

摘要： An apparatus includes a first layer, a second layer under the first layer along an axis, and a metal layer between the first layer and the second layer along the axis. The first layer includes a first plurality of transistors, where a given transistor of the first plurality of transistors includes a gate region; and the second layer includes a second plurality of transistors. The metal layer includes a metal below the gate region, and the metal is within thirty nanometers (nm) of the gate region.

公开(公告)号：US20210193802A1

公开(公告)日：2021-06-24

申请号：US16719415

申请日：2019-12-18

申请人： Intel Corporation

发明人： Aaron D. Lilak ,  Kerryann Marrietta Foley ,  Sayed Hasan ,  Patrick Morrow ,  Willy Rachmady

IPC分类号： H01L29/10 ,  H01L27/12 ,  H01L29/78 ,  H01L29/66 ,  H05K1/18

摘要： Disclosed herein are PN-body-tied field effect transistors (PNBTFETs), as well as related devices and methods. In some embodiments, an integrated circuit (IC) structure may include: a fin including a channel region, a contact region, and an intermediate region between the contact region and the channel region, wherein the channel region includes a dopant of a first type, the intermediate region includes a dopant of a second type different from the first type, and the contact region includes a dopant of the first type; a gate that at least partially wraps around the channel region; and a conductive contact in contact with the contact region.

公开(公告)号：US20200303257A1

公开(公告)日：2020-09-24

申请号：US16651116

申请日：2018-01-12

申请人： Intel Corporation

发明人： Aaron D. Lilak ,  Christopher J. Jezewski ,  Willy Rachmady ,  Rishabh Mehandru ,  Gilbert Dewey ,  Anh Phan

IPC分类号： H01L21/8234 ,  H01L29/78

摘要： In an embodiment of the present disclosure, a device structure includes a fin structure, a gate on the fin structure, and a source and a drain on the fin structure, where the gate is between the source and the drain. The device structure further includes an insulator layer having a first insulator layer portion adjacent to a sidewall of the source, a second insulator layer portion adjacent to a sidewall of the drain, and a third insulator layer portion therebetween adjacent to a sidewall of the gate, and two or more stressor materials adjacent to the insulator layer. The stressor materials can be tensile or compressively stressed and may strain a channel under the gate.

公开(公告)号：US10784358B2

公开(公告)日：2020-09-22

申请号：US15747119

申请日：2015-09-25

申请人： Intel Corporation

发明人： Patrick Morrow ,  Rishabh Mehandru ,  Aaron D. Lilak ,  Kimin Jun

IPC分类号： H01L29/417 ,  H01L29/423 ,  H01L27/12 ,  H01L29/78 ,  H01L29/66 ,  H01L21/8234 ,  H01L29/08 ,  H01L29/40 ,  H01L21/225 ,  H01L21/265

摘要： An apparatus including a circuit structure including a device stratum including a plurality of devices including a first side and an opposite second side; and a metal interconnect coupled to at least one of the plurality of devices from the second side of the device stratum. A method including forming a transistor device including a channel between a source region and a drain region and a gate electrode on the channel defining a first side of the device; and forming an interconnect to one of the source region and the drain region from a second side of the device.

公开(公告)号：US20200295003A1

公开(公告)日：2020-09-17

申请号：US16354960

申请日：2019-03-15

申请人： INTEL CORPORATION

发明人： Gilbert W. Dewey ,  Jack T. Kavalieros ,  Willy Rachmady ,  Cheng-Ying Huang ,  Matthew V. Metz ,  Kimin Jun ,  Patrick Morrow ,  Aaron D. Lilak ,  Ehren Mannebach ,  Anh Phan

IPC分类号： H01L27/092 ,  H01L29/16 ,  H01L29/20 ,  H01L29/06 ,  H01L29/78 ,  H01L21/8238 ,  H01L25/065 ,  H01L23/00 ,  H01L23/31 ,  H01L23/538 ,  H01L29/10

摘要： Disclosed herein are stacked transistors having device strata with different channel widths, as well as related methods and devices. In some embodiments, an integrated circuit structure may include stacked strata of transistors, wherein different channel materials of different strata have different widths.

公开(公告)号：US20200258778A1

公开(公告)日：2020-08-13

申请号：US16274758

申请日：2019-02-13

申请人： INTEL CORPORATION

发明人： Aaron D. Lilak ,  Ehren Mannebach ,  Anh Phan ,  Richard Schenker ,  Stephanie A. Bojarski ,  Willy Rachmady ,  Patrick Morrow ,  Jeffery Bielefeld ,  Gilbert Dewey ,  Hui Jae Yoo ,  Nafees Kabir

IPC分类号： H01L21/768 ,  H01L29/78 ,  H01L29/66 ,  H01L27/092 ,  H01L23/522 ,  H01L21/02 ,  H01L21/8238

摘要： In some embodiments, a semiconductor device structure is formed by using an angled etch to remove material so as to expose a portion of an adjacent conductor. The space formed upon removing the material can then be filled with a conductive material during formation of a contact or other conductive structure (e.g., and interconnection). In this way, the contact formation also fills the space to form an angled local interconnect portion that connects adjacent structures (e.g., a source/drain contact to an adjacent source/drain contact, a source/drain contact to an adjacent gate contact, a source/drain contact to an adjacent device level conductor also connected to a gate/source/drain contact). In other embodiments, an interconnection structure herein termed a “jogged via” establishes and electrical connection from laterally adjacent peripheral surfaces of conductive structures that are not coaxially or concentrically aligned with one another.

公开(公告)号：US20200235134A1

公开(公告)日：2020-07-23

申请号：US16650795

申请日：2017-12-27

申请人： Intel Corporation

发明人： Aaron D. Lilak ,  Rishabh Mehandru ,  Gilbert Dewey ,  Willy Rachmady ,  Anh Phan

IPC分类号： H01L27/12 ,  H01L25/065 ,  H01L21/822 ,  H01L27/06 ,  H01L21/8234 ,  H01L29/78

摘要： Integrated circuits with stacked transistors and methods of manufacturing the same are disclosed. An example integrated circuit includes a first transistor in a first portion of the integrated circuit, and a second transistor stacked above the first transistor and in a second portion of the integrated circuit above the first portion. The integrated circuit further includes a bonding layer between the first and second vertical portions of the integrated circuit. The bonding layer includes an opening extending therethrough between the first and second vertical portions of the integrated circuit. The integrated circuit also includes a gate dielectric on an inner wall of the opening.

公开(公告)号：US20200235092A1

公开(公告)日：2020-07-23

申请号：US16647688

申请日：2018-01-08

申请人： INTEL CORPORATION

发明人： Aaron D. Lilak ,  Cheng-ying Huang ,  Gilbert Dewey ,  Willy Rachmady ,  Rishabh Mehandru

IPC分类号： H01L27/06 ,  H01L21/822 ,  H01L21/8238 ,  H01L27/092 ,  H01L27/12 ,  H01L29/06 ,  H01L29/775 ,  H01L29/786

摘要： An integrated circuit structure includes: a top semiconductor fin extending in a length direction; a bottom semiconductor fin extending in the length direction, the bottom semiconductor fin being under and vertically aligned with the top semiconductor fin; a top gate structure in contact with a portion of the top semiconductor fin; top source and drain regions each adjacent to the portion of the top semiconductor fin; a bottom gate structure in contact with a portion of the bottom semiconductor fin; and bottom source and drain regions each adjacent to the portion of the bottom semiconductor fin. The portion of the top semiconductor fin is between the top source region and the top drain region. The portion of the bottom semiconductor fin is between the bottom source and drain regions. Heights, widths, or both the heights and widths of the portions of the top and bottom semiconductor fins are different.

公开(公告)号：US20200161298A1

公开(公告)日：2020-05-21

申请号：US16615378

申请日：2017-07-01

申请人： Intel Corporation

发明人： Aaron D. Lilak ,  Rishabh Mehandru ,  Patrick Morrow ,  Stephen M. Cea

IPC分类号： H01L27/088 ,  H01L27/06 ,  H01L23/532 ,  H01L23/528 ,  H01L29/78 ,  H01L21/8234

摘要： Metallization structures under a semiconductor device layer. A metallization structure in alignment with semiconductor fin may be on a side of the fin opposite a gate stack. Backside and/or frontside substrate processing techniques may be employed to form such metallization structures on a bottom of a semiconductor fin or between bottom portions of two adjacent fins. Such metallization structures may accompany interconnect metallization layers that are over a gate stack, for example to increase metallization layer density for a given number of semiconductor device layers.

公开(公告)号：US10468489B2

公开(公告)日：2019-11-05

申请号：US15747719

申请日：2015-09-25

申请人： Intel Corporation

发明人： Aaron D. Lilak ,  Uygar E. Avci ,  David L. Kencke ,  Patrick Morrow ,  Kerryann Foley ,  Stephen M. Cea ,  Rishabh Mehandru

IPC分类号： H01L29/417 ,  H01L21/84 ,  H01L27/12 ,  H01L29/78

摘要： Techniques and mechanisms to provide insulation for a component of an integrated circuit device. In an embodiment, structures of a circuit component are formed in or on a first side of a semiconductor substrate, the structures including a first doped region, a second doped region and a third region between the first doped region and the second doped region. The substrate has formed therein an insulation structure, proximate to the circuit component structures, which is laterally constrained to extend only partially from a location under the circuit component toward an edge of the substrate. In another embodiment, a second side of the substrate—opposite the first side—is exposed by thinning to form the substrate from a wafer. Such thinning enables subsequent back side processing to form a recess in the second side, and to deposit the insulation structure in the recess.