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47 条记录 (耗时 0.026 秒)

    LOW CONTENTION CURRENT CIRCUITS
    23.
    发明公开
    LOW CONTENTION CURRENT CIRCUITS 审中-公开

    公开(公告)号：US20240356552A1

    公开(公告)日：2024-10-24

    申请号：US18305147

    申请日：2023-04-21

    申请人： Intel Corporation

    发明人： Steven Hsu ,  Amit Agarwal ,  Ram Krishnamurthy

    IPC分类号： H03K19/0185 ,  G06F3/06 ,  G11C11/418 ,  G11C11/419 ,  H03K19/21

    CPC分类号： H03K19/018521 ,  G06F3/0604 ,  G06F3/0655 ,  G06F3/0679 ,  G11C11/418 ,  G11C11/419 ,  H03K19/21

    摘要： A disclosed example includes a read local bitline; and a plurality of pulldown transistor circuits coupled to the read local bitline, a first one of the pulldown transistor circuits including: a first low threshold voltage transistor, the first low threshold voltage transistor including a first drain terminal coupled to the read local bitline; and a second low threshold voltage transistor, the second low threshold voltage transistor including a second drain terminal coupled to a first source terminal of the first low threshold voltage transistor, the second low threshold voltage transistor to persist a voltage level detectable at a gate terminal of the second low threshold voltage transistor, the voltage level representative of a bit of information.

    Configurable Storage Circuits And Methods
    24.
    发明公开
    Configurable Storage Circuits And Methods 审中-公开

    公开(公告)号：US20240337692A1

    公开(公告)日：2024-10-10

    申请号：US18746853

    申请日：2024-06-18

    申请人： Intel Corporation

    发明人： Rajiv Kumar ,  Amit Agarwal ,  Steven Hsu ,  Scott Weber

    IPC分类号： G01R31/3185

    CPC分类号： G01R31/318541 ,  G01R31/318572

    摘要： A flip-flop circuit includes first and second storage circuits. The flip-flop circuit is configurable to store first values of a data signal in the first storage circuit in response to rising edges of a clock signal and to store second values of the data signal in the second storage circuit in response to falling edges of the clock signal during a double edge triggered mode. The flip-flop circuit is configurable to store third values of the data signal in the first storage circuit and to output the third values from the first storage circuit in response to the clock signal during a single edge triggered mode.

    HIGH PERFORMANCE FAST MUX-D SCAN FLIP-FLOP
    27.
    发明申请
    HIGH PERFORMANCE FAST MUX-D SCAN FLIP-FLOP 有权

    公开(公告)号：US20220224316A1

    公开(公告)日：2022-07-14

    申请号：US17711638

    申请日：2022-04-01

    申请人： Intel Corporation

    发明人： Amit Agarwal ,  Steven Hsu ,  Simeon Realov ,  Mahesh Kumashikar ,  Ram Krishnamurthy

    IPC分类号： H03K3/037 ,  G01R31/3177 ,  H03K3/038 ,  H03K19/20

    摘要： A fast Mux-D scan flip-flop is provided, which bypasses a scan multiplexer to a master keeper side path, removing delay overhead of a traditional Mux-D scan topology. The design is compatible with simple scan methodology of Mux-D scan, while preserving smaller area and small number of inputs/outputs. Since scan Mux is not in the forward critical path, circuit topology has similar high performance as level-sensitive scan flip-flop and can be easily converted into bare pass-gate version. The new fast Mux-D scan flip-flop combines the advantages of the conventional LSSD and Mux-D scan flip-flop, without the disadvantages of each.

    FUSED VOLTAGE LEVEL SHIFTING LATCH
    28.
    发明申请
    FUSED VOLTAGE LEVEL SHIFTING LATCH 审中-公开

    公开(公告)号：US20190280693A1

    公开(公告)日：2019-09-12

    申请号：US16335092

    申请日：2017-08-30

    申请人： Intel Corporation

    发明人： Steven K. Hsu ,  Amit Agarwal ,  Ram K. Krishnamurthy

    IPC分类号： H03K19/0185 ,  H03K3/037

    摘要： Some embodiments include apparatus and methods using an input stage and an output stage of a circuit. The input stage operates to receive an input signal and a clock signal and to provide an internal signal at an internal node based at least in part on the input signal. The input signal has levels in a first voltage range. The internal signal has levels in a second voltage range greater than the first voltage range. The output stage operates to receive the internal signal, the clock signal, and an additional signal generated based on the input signal. The output stage provides an output signal based at least in part on the input signal and the additional signal. The output signal has a third voltage range greater than the first voltage range.

    Integrated clock gate circuit with embedded NOR
    30.
    发明授权
    Integrated clock gate circuit with embedded NOR 有权

    公开(公告)号：US10177765B2

    公开(公告)日：2019-01-08

    申请号：US15244839

    申请日：2016-08-23

    申请人： Intel Corporation

    发明人： Steven K. Hsu ,  Amit Agarwal ,  Iqbal R. Rajwani ,  Simeon Realov ,  Ram K. Krishnamurthy

    IPC分类号： H03K19/00 ,  H03K19/0944 ,  H03K19/20

    摘要： An apparatus is provided which comprises: a clock node; a test node; an enable node; and an AND-OR-INVERT (AOI) static latch coupled to the clock node, test node, and enable node, wherein the AOI static latch has embedded NOR functionality. Another apparatus comprises: a critical timing path having a pass-gate based integrated clock gate; and a non-critical timing path electrically coupled to the critical timing path, wherein the non-critical timing path includes an AND-OR-Inverter (AOI) based integrated clock gate with embedded NOR functionality.