公开(公告)号：US12107557B2

公开(公告)日：2024-10-01

申请号：US17426065

申请日：2019-10-10

Applicant: INTEL CORPORATION

Inventor： Daniel Gruber ,  Michael Kalcher

IPC: H03F1/22 ,  G05F1/575 ,  G05F1/618 ,  H03F3/45 ,  H03F3/50

CPC classification number: H03F3/505 ,  G05F1/575 ,  G05F1/618 ,  H03F3/45636

Abstract: Examples relate to a buffered flipped voltage follower circuit arrangement, low dropout voltage regulators, a capacitive digital-to-analog converter, a transceiver for wireless communication, a mobile communication device, a base station transceiver, and to a method for forming a buffered flipped voltage follower circuit arrangement. The buffered flipped voltage follower circuit arrangement comprises a first transistor (Mp) comprising a first terminal, a second terminal and a gate terminal. The buffered flipped voltage follower circuit arrangement comprises a second transistor (Mc) comprising a first terminal, a second terminal and a gate terminal. The buffered flipped voltage follower circuit arrangement comprises a buffer circuit comprising an input terminal and an output terminal. The buffered flipped voltage follower circuit arrangement a feed-forward compensation circuit (−gmf) comprising an input terminal and an output terminal. The first terminal of the first transistor (Mp) is coupled to a supply voltage of the flipped voltage follower circuit. The second terminal of the first transistor (Mp) is coupled with the first terminal of the second transistor (Mc) and with an output voltage terminal of the buffered flipped voltage follower circuit arrangement. The second terminal of the second transistor (Mc) is coupled with the input terminal of the buffer circuit and with the output terminal of the feed-forward compensation circuit (−gmf). The gate terminal of the first transistor (MP) is coupled with the output terminal of the buffer circuit and with the input terminal of the feed-forward compensation circuit (−gmf).

公开(公告)号：US12034450B2

公开(公告)日：2024-07-09

申请号：US17754308

申请日：2019-12-27

Applicant: Intel Corporation

Inventor： Daniel Gruber ,  Ramon Sanchez ,  Kameran Azadet ,  Martin Clara

IPC: H03M1/10 ,  H03M1/06

CPC classification number: H03M1/1033 ,  H03M1/0626

Abstract: An apparatus for correcting a mismatch between a first segment and a second segment of a Digital-to-Analog Converter, DAC, is provided. The first segment generates a first contribution to an analog output signal of the DAC based on a first number of bits of a digital input word for the DAC converter, and the second segment generates a second contribution based on a second number of bits. Further, the apparatus comprises a first processing circuit for the first number of bits comprising a first filter configured to modify the first number of bits to generate first modified bits, and a second processing circuit comprising a second filter to modify the second number of bits to generate second modified bits. The apparatus additionally comprises an output configured to output a modified digital input word for the DAC, which is based on the first modified bits and the second modified bits.

公开(公告)号：US12015417B2

公开(公告)日：2024-06-18

申请号：US17131868

申请日：2020-12-23

Applicant: Intel Corporation

Inventor： Daniel Gruber ,  Matteo Camponeschi ,  Christian Lindholm ,  Martin Clara ,  Giacomo Cascio

IPC: H03M1/06 ,  H03K3/02 ,  H04B1/16

CPC classification number: H03M1/0609 ,  H03K3/02 ,  H04B1/16

Abstract: An input buffer circuit for an analog-to-digital converter is provided. The input buffer circuit includes a buffer amplifier. The buffer amplifier includes a first input node and a second input node each configured to receive a respective one of a first input signal and a second input signal forming a differential input signal pair for the analog-to-digital converter. The buffer amplifier further includes a first output node and a second output node each configured to output a respective one of a first buffered signal and a second buffered signal. In addition, the input buffer circuit includes feedback circuitry. The feedback circuitry is configured to generate, based on the first buffered signal and the second buffered signal, a first feedback signal and a second feedback signal for mitigating a respective unwanted signal component at the first input node and the second input node related to a limited reverse isolation of the amplifier buffer. The feedback circuitry is further configured to supply the first feedback signal to the first input node and the second feedback signal to the second input node.

公开(公告)号：US11901908B2

公开(公告)日：2024-02-13

申请号：US17754148

申请日：2019-12-23

Applicant: Intel Corporation

Inventor： Daniel Gruber ,  Kameran Azadet ,  Yu-Shan Wang ,  Hundo Shin ,  Martin Clara

IPC: H04B1/04 ,  H03M1/06 ,  H04B1/10

CPC classification number: H03M1/0614 ,  H04B1/0475 ,  H04B1/1018

Abstract: A Digital-to-Analog Converter, DAC, is provided. The DAC comprises one or more first DAC cells configured to generate a first analog signal based on first digital data. The one or more first DAC cells are coupled to a first output node for coupling to a first load. The DAC comprises one or more second DAC cells configured to generate a second analog signal based on second digital data. The one or more second DAC cells are coupled to a second output node for coupling to a second load. The one or more first DAC cells and the one or more second DAC cells are couplable to a power supply for drawing a supply current. The DAC further comprises a data generation circuit configured to generate the second digital data based on the first digital data.

公开(公告)号：US11637560B2

公开(公告)日：2023-04-25

申请号：US17455221

申请日：2021-11-17

Applicant: Intel Corporation

Inventor： Martin Clara ,  Daniel Gruber ,  Kameran Azadet

IPC: H03M1/20 ,  H03M1/10

Abstract: A segmented digital-to-analog converter (DAC) includes DAC segments, an overrange DAC, and a dither control circuit. Each DAC segment includes a plurality of DAC cells for generating an analog output signal based on input data to each DAC segment. The overrange DAC generates an analog output signal based on a control signal. The dither control circuit adds a dither to first input data supplied to a higher-order DAC segment, subtract a portion of the dither from second input data supplied to a lower-order DAC segment, and generate the control signal for subtracting a remaining portion of the dither from an output of the segmented DAC in an analog domain. The dither added to the first input data may be one of +1, 0, and −1 and the portion of the dither subtracted from the second input data may be a half of the dither added to the first input data.

公开(公告)号：US11378999B2

公开(公告)日：2022-07-05

申请号：US16724486

申请日：2019-12-23

Applicant: Intel Corporation

Inventor： Yu-Shan Wang ,  Martin Clara ,  Daniel Gruber ,  Hundo Shin ,  Kameran Azadet

IPC: G06F1/12 ,  G06F1/14 ,  G06F1/08

Abstract: An apparatus for generating synchronized clock signals is provided. The apparatus comprises a first circuit comprising a clock divider circuit configured to receive a first clock signal and to generate a second clock signal by frequency dividing the first clock signal. Further, the apparatus comprises a one or more second circuits comprising a respective synchronization circuit configured to receive the first clock signal. The synchronization circuit of one of the one or more second circuits is configured to receive the second clock signal from the first circuit and to resample the second clock signal based on the first clock signal in order to generate a replica of the second clock signal that is in phase with the second clock signal.

公开(公告)号：US11239866B2

公开(公告)日：2022-02-01

申请号：US16924274

申请日：2020-07-09

Applicant: Intel Corporation

Inventor： Daniel Gruber ,  Ramon Sanchez ,  Kameran Azadet ,  Martin Clara

IPC: H04B1/00 ,  H04B1/04 ,  H03M1/66 ,  H04B1/10

Abstract: A digital-to-analog conversion system is provided. The digital-to-analog conversion system includes a digital-to-analog converter configured to receive a pre-distorted digital signal from a digital circuit, and to generate an analog signal based on the pre-distorted digital signal. Further, the digital-to-analog conversion system includes a feedback loop for providing a digital feedback signal to the digital circuit. The feedback loop includes an analog-to-digital converter configured to generate the digital feedback signal based on the analog signal, and wherein a sample rate of the analog-to-digital converter is lower than a sample rate of the digital-to-analog converter.

公开(公告)号：US11044137B1

公开(公告)日：2021-06-22

申请号：US16724458

申请日：2019-12-23

Applicant: Intel Corporation

Inventor： Kameran Azadet ,  Martin Clara ,  Daniel Gruber ,  Christian Lindholm ,  Hundo Shin

IPC: H03M1/36 ,  H04L27/36 ,  H03M1/06 ,  H03M1/10 ,  H04B1/04

Abstract: An Analog-to-Digital Converter, ADC, system is provided. The ADC system comprises a plurality of ADC circuits and a first input for receiving a transmit signal of a transceiver. One ADC circuit of the plurality of ADC circuits is coupled to the first input and configured to provide first digital data based on the transmit signal. The ADC system further comprises a second input for receiving a receive signal of the transceiver. The other ADC circuits of the plurality of ADC circuits are coupled to the second input, wherein the other ADC circuits of the plurality of ADC circuits are time-interleaved and configured to provide second digital data based on the receive signal. Additionally, the ADC system comprises a first output configured to output digital feedback data based on the first digital data, and a second output configured to output digital receive data based on the second digital data.