中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

117 records (took 0.027 seconds)

    NETWORK INTERFACE DEVICE FAILOVER
    23.
    发明公开
    NETWORK INTERFACE DEVICE FAILOVER 审中-公开

    公开(公告)号：US20230393956A1

    公开(公告)日：2023-12-07

    申请号：US18230387

    申请日：2023-08-04

    Applicant: Intel Corporation

    Inventor： Francesc GUIM BERNAT ,  Eoin WALSH ,  Karthik KUMAR ,  Marcos E. CARRANZA

    IPC: G06F11/20

    CPC classification number: G06F11/2002

    Abstract: Examples described herein relate to failover of processes from a first network interface device to a second network interface device. A first programmable network interface device includes a network interface, a direct memory access (DMA) circuitry, a host interface, and at least one processor to execute a first process. A second programmable network interface device includes a network interface, a DMA circuitry, a host interface, and at least one processor. The at least one processor of the second programmable network interface device is to perform failover execution of the first process.

    REMOTE STORAGE FOR HARDWARE MICROSERVICES HOSTED ON XPUS AND SOC-XPU PLATFORMS
    26.
    发明申请
    REMOTE STORAGE FOR HARDWARE MICROSERVICES HOSTED ON XPUS AND SOC-XPU PLATFORMS 有权

    公开(公告)号：US20220113911A1

    公开(公告)日：2022-04-14

    申请号：US17558268

    申请日：2021-12-21

    Applicant: Intel Corporation

    Inventor： Andrzej KURIATA ,  Susanne M. BALLE ,  Duane E. GALBI ,  Sundar NADATHUR ,  Nagabhushan CHITLUR ,  Francesc GUIM BERNAT ,  Alexander BACHMUTSKY

    IPC: G06F3/06 ,  G06F15/78

    Abstract: Methods, apparatus, and software for remote storage of hardware microservices hosted on other processing units (XPUs) and SOC-XPU Platforms. The apparatus may be a platform including a System on Chip (SOC) and an XPU, such as a Field Programmable Gate Array (FPGA). Software, via execution on the SOC, enables the platform to pre-provision storage space on a remote storage node and assign the storage space to the platform, wherein the pre-provisioned storage space includes one or more container images to be implemented as one or more hardware (HW) microservice front-ends. The XPU/FPGA is configured to implement one or more accelerator functions used to accelerate HW microservice backend operations that are offloaded from the one or more HW microservice front-ends. The platform is also configured to pre-provision a remote storage volume containing worker node components and access and persistently store worker node components.

    MEMORY POOL DATA PLACEMENT TECHNOLOGIES
    27.
    发明申请
    MEMORY POOL DATA PLACEMENT TECHNOLOGIES 有权

    公开(公告)号：US20220004330A1

    公开(公告)日：2022-01-06

    申请号：US17480938

    申请日：2021-09-21

    Applicant: Intel Corporation

    Inventor： Francesc GUIM BERNAT ,  Karthik KUMAR

    IPC: G06F3/06 ,  G06F13/16

    Abstract: Examples described herein relate to a network interface device, when operational, configured to: select data of a region of addressable memory addresses to migrate from a first memory pool to a second memory pool to lower a transit time of the data of the region of addressable memory addresses to a computing platform. In some examples, selecting data of a region of addressable memory addresses to migrate from a first memory pool to a second memory pool is based at least, in part, on one or more of: (a) memory bandwidth used to access the data; (b) latency to access the data from the first memory pool by the computing platform; (c) number of accesses to the data over a window of time by the computing platform; (d) number of accesses to the data over a window of time by other computing platforms over a window of time; (e) historic congestion to and/or from one or more memory pools accessible to the computing platform; and/or (f) number of different computing platforms that access the data.

    DATA MANAGEMENT FOR EDGE ARCHITECTURES
    28.
    发明申请
    DATA MANAGEMENT FOR EDGE ARCHITECTURES 有权

    公开(公告)号：US20210373954A1

    公开(公告)日：2021-12-02

    申请号：US17401652

    申请日：2021-08-13

    Applicant: Intel Corporation

    Inventor： Francesc GUIM BERNAT ,  Ramanathan SETHURAMAN ,  Karthik KUMAR ,  Mark A. SCHMISSEUR ,  Brinda GANESH

    IPC: G06F9/50 ,  G06F9/54

    Abstract: Data management for edge architected computing systems extends current storage and memory schemes of edge resources to expose interfaces to allow a device, such as an endpoint or client device, or another edge resource, to specify criteria for managing data originating from the device and stored in an edge resource, and extends the storage and memory controllers to manage data in accordance with the criteria, including removing stored data that no longer satisfies the criteria. The criteria includes a temporal hint to specify a time after which the data can be removed, a physical hint to specify a list of edge resources outside of which the data can be removed, an event-based hint to specify an event after which the data can be removed, and a quality of service condition to modify the time specified in the temporal hint based on a condition, such as memory and storage capacity of the edge resource in which the data is managed.

Patent Agency Ranking