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1.
公开(公告)号:US20180227963A1
公开(公告)日:2018-08-09
申请号:US15748580
申请日:2015-11-23
Applicant: Intel Corporation
Inventor: Telesphor KAMGAING , Rahul KHANNA
CPC classification number: H04W76/10 , H01L23/66 , H01L24/16 , H01L24/17 , H01L24/73 , H01L25/0655 , H01L25/0657 , H01L25/16 , H01L2223/6616 , H01L2223/6677 , H01L2223/6683 , H01L2223/6688 , H01L2224/16221 , H01L2224/16235 , H01L2224/73253 , H01L2225/06517 , H01L2225/0652 , H01L2225/06548 , H01L2225/06572 , H01L2225/06589 , H01L2924/10253 , H01L2924/10329 , H01L2924/1033 , H01L2924/1421 , H01L2924/1432 , H01L2924/1434 , H01L2924/15153 , H01L2924/15192 , H01L2924/15311 , H01L2924/15313 , H01L2924/15321 , H01L2924/19105 , H01Q1/2266 , H01Q1/2283 , H01Q3/30 , H04B1/38 , H04B1/48 , H04Q1/15 , H05K7/1487
Abstract: A blade computing system is described with a wireless communication between blades. In one embodiment, the system includes a first blade in the enclosure having a radio transceiver to communicate with a radio transceiver of a second blade in the enclosure. The second blade has a radio transceiver to communicate with the radio transceiver of the first blade. A switch in the enclosure communicates with the first blade and the second blade and establishes a connection through the respective radio transceivers between the first blade and the second blade.
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公开(公告)号:US20210314245A1
公开(公告)日:2021-10-07
申请号:US17235135
申请日:2021-04-20
Applicant: Intel Corporation
Inventor: Francesc GUIM BERNAT , Susanne M. BALLE , Rahul KHANNA , Sujoy SEN , Karthik KUMAR
IPC: H04L12/26 , G06F16/901 , H04B10/25 , G02B6/38 , G02B6/42 , G02B6/44 , G06F1/18 , G06F1/20 , G06F3/06 , G06F8/65 , G06F9/30 , G06F9/4401 , G06F9/54 , G06F12/109 , G06F12/14 , G06F13/16 , G06F13/40 , G08C17/02 , G11C5/02 , G11C7/10 , G11C11/56 , G11C14/00 , H03M7/30 , H03M7/40 , H04L12/24 , H04L12/931 , H04L12/947 , H04L29/08 , H04L29/06 , H04Q11/00 , H05K7/14 , G06F15/16
Abstract: Technologies for dynamically managing resources in disaggregated accelerators include an accelerator. The accelerator includes acceleration circuitry with multiple logic portions, each capable of executing a different workload. Additionally, the accelerator includes communication circuitry to receive a workload to be executed by a logic portion of the accelerator and a dynamic resource allocation logic unit to identify a resource utilization threshold associated with one or more shared resources of the accelerator to be used by a logic portion in the execution of the workload, limit, as a function of the resource utilization threshold, the utilization of the one or more shared resources by the logic portion as the logic portion executes the workload, and subsequently adjust the resource utilization threshold as the workload is executed. Other embodiments are also described and claimed.
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公开(公告)号:US20210105197A1
公开(公告)日:2021-04-08
申请号:US17086206
申请日:2020-10-30
Applicant: Intel Corporation
Inventor: Susanne M. BALLE , Rahul KHANNA , Nishi AHUJA , Mrittika GANGULI
IPC: H04L12/26 , G06F16/901 , H04B10/25 , G02B6/38 , G02B6/42 , G02B6/44 , G06F1/18 , G06F1/20 , G06F3/06 , G06F8/65 , G06F9/30 , G06F9/4401 , G06F9/54 , G06F12/109 , G06F12/14 , G06F13/16 , G06F13/40 , G08C17/02 , G11C5/02 , G11C7/10 , G11C11/56 , G11C14/00 , H03M7/30 , H03M7/40 , H04L12/24 , H04L12/931 , H04L12/947 , H04L29/08 , H04L29/06 , H04Q11/00 , H05K7/14
Abstract: Technologies for allocating resources of managed nodes to workloads to balance multiple resource allocation objectives include an orchestrator server to receive resource allocation objective data indicative of multiple resource allocation objectives to be satisfied. The orchestrator server is additionally to determine an initial assignment of a set of workloads among the managed nodes and receive telemetry data from the managed nodes. The orchestrator server is further to determine, as a function of the telemetry data and the resource allocation objective data, an adjustment to the assignment of the workloads to increase an achievement of at least one of the resource allocation objectives without decreasing an achievement of another of the resource allocation objectives, and apply the adjustments to the assignments of the workloads among the managed nodes as the workloads are performed. Other embodiments are also described and claimed.
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公开(公告)号:US20240113954A1
公开(公告)日:2024-04-04
申请号:US18388461
申请日:2023-11-09
Applicant: Intel Corporation
Inventor: Francesc GUIM BERNAT , Susanne M. BALLE , Rahul KHANNA , Sujoy SEN , Karthik KUMAR
IPC: H04L43/08 , G02B6/38 , G02B6/42 , G02B6/44 , G06F1/18 , G06F1/20 , G06F3/06 , G06F8/65 , G06F9/30 , G06F9/4401 , G06F9/54 , G06F12/109 , G06F12/14 , G06F13/16 , G06F13/40 , G06F15/16 , G06F16/901 , G08C17/02 , G11C5/02 , G11C7/10 , G11C11/56 , G11C14/00 , H03M7/30 , H03M7/40 , H04B10/25 , H04L41/14 , H04L43/0817 , H04L43/0876 , H04L43/0894 , H04L49/00 , H04L49/25 , H04L49/356 , H04L49/45 , H04L67/02 , H04L67/306 , H04L69/04 , H04L69/329 , H04Q11/00 , H05K7/14
CPC classification number: H04L43/08 , G02B6/3882 , G02B6/3893 , G02B6/3897 , G02B6/4292 , G02B6/4452 , G06F1/183 , G06F1/20 , G06F3/0613 , G06F3/0625 , G06F3/064 , G06F3/0653 , G06F3/0655 , G06F3/0664 , G06F3/0665 , G06F3/0673 , G06F3/0679 , G06F3/0683 , G06F3/0688 , G06F3/0689 , G06F8/65 , G06F9/30036 , G06F9/4401 , G06F9/544 , G06F12/109 , G06F12/1408 , G06F13/1668 , G06F13/4022 , G06F13/4068 , G06F13/409 , G06F15/161 , G06F16/9014 , G08C17/02 , G11C5/02 , G11C7/1072 , G11C11/56 , G11C14/0009 , H03M7/3086 , H03M7/4056 , H03M7/4081 , H04B10/25891 , H04L41/145 , H04L43/0817 , H04L43/0876 , H04L43/0894 , H04L49/00 , H04L49/25 , H04L49/357 , H04L49/45 , H04L67/02 , H04L67/306 , H04L69/04 , H04L69/329 , H04Q11/0003 , H05K7/1442 , B25J15/0014
Abstract: Technologies for dynamically managing resources in disaggregated accelerators include an accelerator. The accelerator includes acceleration circuitry with multiple logic portions, each capable of executing a different workload. Additionally, the accelerator includes communication circuitry to receive a workload to be executed by a logic portion of the accelerator and a dynamic resource allocation logic unit to identify a resource utilization threshold associated with one or more shared resources of the accelerator to be used by a logic portion in the execution of the workload, limit, as a function of the resource utilization threshold, the utilization of the one or more shared resources by the logic portion as the logic portion executes the workload, and subsequently adjust the resource utilization threshold as the workload is executed. Other embodiments are also described and claimed.
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公开(公告)号:US20210334138A1
公开(公告)日:2021-10-28
申请号:US17365898
申请日:2021-07-01
Applicant: Intel Corporation
Inventor: Francesc GUIM BERNAT , Susanne M. BALLE , Slawomir PUTYRSKI , Rahul KHANNA , Paul DORMITZER
Abstract: Technologies for pre-configuring accelerators by predicting bit-streams include communication circuitry and a compute device. The compute device includes a compute engine to determine one or more bit-streams registered on each accelerator of multiple accelerators. The compute engine is further to predict a next job to be requested for acceleration from an application of at least one compute sled of multiple compute sleds, predict a bit-stream from a bit-stream library that is to execute the predicted next job requested to be accelerated, and determine whether the predicted bit-stream is already registered on one of the accelerators. In response to a determination that the predicted bit-stream is not registered on one of the accelerators, the compute engine is to select an accelerator from the plurality of accelerators that satisfies characteristics of the predicted bit-stream and register the predicted bit-stream on the determined accelerator.
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公开(公告)号:US20220321438A1
公开(公告)日:2022-10-06
申请号:US17733086
申请日:2022-04-29
Applicant: Intel Corporation
Inventor: Francesc GUIM BERNAT , Susanne M. BALLE , Rahul KHANNA , Sujoy SEN , Karthik KUMAR
IPC: H04L43/08 , G06F16/901 , H04B10/25 , G02B6/38 , G02B6/42 , G02B6/44 , G06F1/18 , G06F1/20 , G06F3/06 , G06F8/65 , G06F9/30 , G06F9/4401 , G06F9/54 , G06F12/109 , G06F12/14 , G06F13/16 , G06F13/40 , G08C17/02 , G11C5/02 , G11C7/10 , G11C11/56 , G11C14/00 , H03M7/30 , H03M7/40 , H04L41/14 , H04L43/0817 , H04L43/0876 , H04L43/0894 , H04L49/00 , H04L49/25 , H04L49/356 , H04L49/45 , H04L67/02 , H04L67/306 , H04L69/04 , H04L69/329 , H04Q11/00 , H05K7/14 , G06F15/16
Abstract: Technologies for dynamically managing resources in disaggregated accelerators include an accelerator. The accelerator includes acceleration circuitry with multiple logic portions, each capable of executing a different workload. Additionally, the accelerator includes communication circuitry to receive a workload to be executed by a logic portion of the accelerator and a dynamic resource allocation logic unit to identify a resource utilization threshold associated with one or more shared resources of the accelerator to be used by a logic portion in the execution of the workload, limit, as a function of the resource utilization threshold, the utilization of the one or more shared resources by the logic portion as the logic portion executes the workload, and subsequently adjust the resource utilization threshold as the workload is executed. Other embodiments are also described and claimed.
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7.
公开(公告)号:US20200045754A1
公开(公告)日:2020-02-06
申请号:US16600276
申请日:2019-10-11
Applicant: Intel Corporation
Inventor: Telesphor KAMGAING , Rahul KHANNA
IPC: H04W76/10 , H01L25/065 , H01L25/16 , H01L23/66 , H01Q1/22 , H04B1/48 , H01L23/00 , H04Q1/02 , H05K7/14
Abstract: A blade computing system is described with a wireless communication between blades. In one embodiment, the system includes a first blade in the enclosure having a radio transceiver to communicate with a radio transceiver of a second blade in the enclosure. The second blade has a radio transceiver to communicate with the radio transceiver of the first blade. A switch in the enclosure communicates with the first blade and the second blade and establishes a connection through the respective radio transceivers between the first blade and the second blade.
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