公开(公告)号：US20220321438A1

公开(公告)日：2022-10-06

申请号：US17733086

申请日：2022-04-29

Applicant: Intel Corporation

Inventor： Francesc GUIM BERNAT ,  Susanne M. BALLE ,  Rahul KHANNA ,  Sujoy SEN ,  Karthik KUMAR

IPC: H04L43/08 ,  G06F16/901 ,  H04B10/25 ,  G02B6/38 ,  G02B6/42 ,  G02B6/44 ,  G06F1/18 ,  G06F1/20 ,  G06F3/06 ,  G06F8/65 ,  G06F9/30 ,  G06F9/4401 ,  G06F9/54 ,  G06F12/109 ,  G06F12/14 ,  G06F13/16 ,  G06F13/40 ,  G08C17/02 ,  G11C5/02 ,  G11C7/10 ,  G11C11/56 ,  G11C14/00 ,  H03M7/30 ,  H03M7/40 ,  H04L41/14 ,  H04L43/0817 ,  H04L43/0876 ,  H04L43/0894 ,  H04L49/00 ,  H04L49/25 ,  H04L49/356 ,  H04L49/45 ,  H04L67/02 ,  H04L67/306 ,  H04L69/04 ,  H04L69/329 ,  H04Q11/00 ,  H05K7/14 ,  G06F15/16

Abstract: Technologies for dynamically managing resources in disaggregated accelerators include an accelerator. The accelerator includes acceleration circuitry with multiple logic portions, each capable of executing a different workload. Additionally, the accelerator includes communication circuitry to receive a workload to be executed by a logic portion of the accelerator and a dynamic resource allocation logic unit to identify a resource utilization threshold associated with one or more shared resources of the accelerator to be used by a logic portion in the execution of the workload, limit, as a function of the resource utilization threshold, the utilization of the one or more shared resources by the logic portion as the logic portion executes the workload, and subsequently adjust the resource utilization threshold as the workload is executed. Other embodiments are also described and claimed.

公开(公告)号：US20220004330A1

公开(公告)日：2022-01-06

申请号：US17480938

申请日：2021-09-21

Applicant: Intel Corporation

Inventor： Francesc GUIM BERNAT ,  Karthik KUMAR

IPC: G06F3/06 ,  G06F13/16

Abstract: Examples described herein relate to a network interface device, when operational, configured to: select data of a region of addressable memory addresses to migrate from a first memory pool to a second memory pool to lower a transit time of the data of the region of addressable memory addresses to a computing platform. In some examples, selecting data of a region of addressable memory addresses to migrate from a first memory pool to a second memory pool is based at least, in part, on one or more of: (a) memory bandwidth used to access the data; (b) latency to access the data from the first memory pool by the computing platform; (c) number of accesses to the data over a window of time by the computing platform; (d) number of accesses to the data over a window of time by other computing platforms over a window of time; (e) historic congestion to and/or from one or more memory pools accessible to the computing platform; and/or (f) number of different computing platforms that access the data.

公开(公告)号：US20210373954A1

公开(公告)日：2021-12-02

申请号：US17401652

申请日：2021-08-13

Applicant: Intel Corporation

Inventor： Francesc GUIM BERNAT ,  Ramanathan SETHURAMAN ,  Karthik KUMAR ,  Mark A. SCHMISSEUR ,  Brinda GANESH

IPC: G06F9/50 ,  G06F9/54

Abstract: Data management for edge architected computing systems extends current storage and memory schemes of edge resources to expose interfaces to allow a device, such as an endpoint or client device, or another edge resource, to specify criteria for managing data originating from the device and stored in an edge resource, and extends the storage and memory controllers to manage data in accordance with the criteria, including removing stored data that no longer satisfies the criteria. The criteria includes a temporal hint to specify a time after which the data can be removed, a physical hint to specify a list of edge resources outside of which the data can be removed, an event-based hint to specify an event after which the data can be removed, and a quality of service condition to modify the time specified in the temporal hint based on a condition, such as memory and storage capacity of the edge resource in which the data is managed.

公开(公告)号：US20210326299A1

公开(公告)日：2021-10-21

申请号：US17363867

申请日：2021-06-30

Applicant: Intel Corporation

Inventor： Francesc GUIM BERNAT ,  Karthik KUMAR ,  Mustafa HAJEER

IPC: G06F15/173 ,  H04L29/08 ,  H04L29/06 ,  G06F15/167

Abstract: An apparatus is described. The apparatus includes logic circuitry embedded in at least one of a memory controller, network interface and peripheral control hub to process a function as a service (FaaS) function call embedded in a request. The request is formatted according to a protocol. The protocol allows a remote computing system to access a memory that is coupled to the memory controller without invoking processing cores of a local computing system that the memory controller is a component of.

公开(公告)号：US20210073138A1

公开(公告)日：2021-03-11

申请号：US16950233

申请日：2020-11-17

Applicant: Intel Corporation

Inventor： Karthik KUMAR ,  Thomas WILLHALM ,  Francesc GUIM BERNAT ,  Brian J. SLECHTA

IPC: G06F12/0891 ,  G06F9/30

Abstract: Embodiments of the invention include a machine-readable medium having stored thereon at least one instruction, which if performed by a machine causes the machine to perform a method that includes decoding, with a node, an invalidate instruction; and executing, with the node, the invalidate instruction for invalidating a memory range specified across a fabric interconnect.

公开(公告)号：US20200379922A1

公开(公告)日：2020-12-03

申请号：US16995481

申请日：2020-08-17

Applicant: Intel Corporation

Inventor： Karthik KUMAR ,  Francesc GUIM BERNAT

IPC: G06F12/14 ,  G06F12/0813 ,  G06F12/0891 ,  G06F12/06

Abstract: Examples described herein relate to a network device apparatus that includes a packet processing circuitry configured to determine if target data associated with a memory access request is stored in a different device than that identified in the memory access request and based on the target data associated with the memory access request identified as stored in a different device than that identified in the memory access request, cause transmission of the memory access request to the different device. In some examples, the memory access request comprises an identifier of a requester of the memory access request and the identifier comprises a Process Address Space identifier (PASID) and wherein the configuration that a redirection operation is permitted to be performed for a memory access request is based at least on the identifier. In some examples, the packet processing circuitry is to: based on configuration of a redirection operation not to be performed for the memory access request, cause transmission of the memory access request to a device identified in the memory access request.

公开(公告)号：US20190102090A1

公开(公告)日：2019-04-04

申请号：US15719729

申请日：2017-09-29

Applicant: Intel Corporation

Inventor： Francesc GUIM BERNAT ,  Karthik KUMAR ,  Thomas WILLHALM ,  Mark SCHMISSEUR

IPC: G06F3/06 ,  G06F9/48

Abstract: A memory controller method and apparatus, which includes a modification of at least one of a first timing scheme or a second timing scheme based on information about one or more data requests to be included in at least one of a first queue scheduler or a second queue scheduler, the first timing scheme indicating when one or more requests in the first queue scheduler are to be issued to the first memory set via a first memory set interface and over a channel, the second timing scheme indicating when one or more requests in the second queue scheduler are to be issued to the second memory set via a second memory set interface and over the channel. Furthermore, an issuance of a request to at least one of the first memory set in accordance with the modified first timing scheme or the second memory set in accordance with the modified second timing scheme may be included.

公开(公告)号：US20190042372A1

公开(公告)日：2019-02-07

申请号：US16012525

申请日：2018-06-19

Applicant: Intel Corporation

Inventor： Karthik KUMAR ,  Francesc GUIM BERNAT ,  Mark A. SCHMISSEUR ,  Mustafa HAJEER ,  Thomas WILLHALM

IPC: G06F11/14 ,  G06F11/20 ,  H04L29/06 ,  H04L29/08

Abstract: An in-memory database is mirrored in persistent memory in nodes in a computer cluster for redundancy. Data can be recovered from persistent memory in a node that is powered down through the use of out-of-band techniques.

公开(公告)号：US20240248633A1

公开(公告)日：2024-07-25

申请号：US18477573

申请日：2023-09-29

Applicant: Intel Corporation

Inventor： Francesc GUIM BERNAT ,  Karthik KUMAR ,  Marcos CARRANZA ,  Rajesh POORNACHANDRAN ,  Thomas WILLHALM

IPC: G06F3/06

CPC classification number: G06F3/0653 ,  G06F3/0604 ,  G06F3/0683

Abstract: Various examples of the present disclosure relate to apparatuses, devices, methods, and computer programs for providing and processing information characterizing a non-uniform memory architecture. An apparatus for a computer system comprises processing circuitry to determine a presence of one or more memory devices connected to at least one processor of the computer system via a serial communication-based processor-to-memory interface, the one or more memory devices being part of a non-uniform memory architecture used by the computer system, determine at least one characteristic for the one or more memory devices by estimating or measuring a performance of the one or more memory devices as observed by the at least one processor, and provide information on the at least one characteristic of the one or more memory devices as part of information characterizing the non-uniform memory architecture.

公开(公告)号：US20240028505A1

公开(公告)日：2024-01-25

申请号：US18375477

申请日：2023-09-30

Applicant: Intel Corporation

Inventor： Sharanyan SRIKANTHAN ,  Thomas WILLHALM ,  Francesc GUIM BERNAT ,  Karthik KUMAR ,  Marcos E. CARRANZA

IPC: G06F12/02

CPC classification number: G06F12/023

Abstract: Examples described herein relate to allocation of an amount of memory for a time duration based on receipt of a request to allocate an amount of memory for a time duration. The request can include a configuration that requests an allocation of the amount of memory and the configuration specifies a time tier and/or the time duration. The request can specify one or more of: a request identifier, the amount of memory to allocate, or a requested time duration to reserve the amount of memory.