公开(公告)号：US20190220301A1

公开(公告)日：2019-07-18

申请号：US16328062

申请日：2016-09-26

Applicant: INTEL CORPORATION

Inventor： Xiao ZHENG ,  Yao Zu DONG ,  Kun TIAN

IPC: G06F9/455 ,  G06F12/02

CPC classification number: G06F9/45558 ,  G06F12/0292 ,  G06F12/1009 ,  G06F2009/45583 ,  G06F2212/151 ,  G06F2212/50 ,  G06F2212/651 ,  G06F2212/657

Abstract: An apparatus and method are described for implementing a hybrid layer of address mapping for an IOMMU implementation. For example, one embodiment of a graphics processing apparatus comprises: virtualization circuitry to implement a virtualized execution environment in which a plurality of guest virtual machines (VMs) are to execute and share execution resources of the graphics processing apparatus; an input/output (I/O) memory management unit (IOMMU) to couple the VMs to one or more I/O devices; a hybrid layer address mapping (HLAM) module to combine entries from a per-process graphics translation table (PPGTT) with entries from a global graphics translation table (GGTT) into a first integrated page table, the first integrated page table mapping PPGTT guest page numbers (GPNs) to host page numbers (HPNs) and mapping GGTT virtual GPNs to HPNs; the HLAM to transform a GGTT GPN into a virtual GPN usable to access a corresponding HPN within the first integrated page table in response to a GGTT read/write operation generated by a first guest virtual machine (VM).

公开(公告)号：US20190114283A1

公开(公告)日：2019-04-18

申请号：US16211924

申请日：2018-12-06

Applicant: Intel Corporation

Inventor： Manasi DEVAL ,  Nrupal JANI ,  Anjali SINGHAI ,  Parthasarathy SARANGAM ,  Mitu AGGARWAL ,  Neerav PARIKH ,  Kiran PATIL ,  Rajesh M. SANKARAN ,  Sanjay K. KUMAR ,  Utkarsh Y. KAKAIYA ,  Philip LANTZ ,  Kun TIAN

IPC: G06F13/42 ,  G06F9/455

Abstract: Examples may include a computing platform having a host driver to get a packet descriptor of a received packet stored in a receive queue and to modify the packet descriptor from a first format to a second format. The computing platform also includes a guest virtual machine including a guest driver coupled to the host driver, the guest driver to receive the modified packet descriptor and to read a packet buffer stored in the receive queue using the modified packet descriptor, the packet buffer corresponding to the packet descriptor.

公开(公告)号：US20190114195A1

公开(公告)日：2019-04-18

申请号：US16211941

申请日：2018-12-06

Applicant: Intel Corporation

Inventor： Nrupal JANI ,  Manasi DEVAL ,  Anjali SINGHAI ,  Parthasarathy SARANGAM ,  Mitu AGGARWAL ,  Neerav PARIKH ,  Alexander H. DUYCK ,  Kiran PATIL ,  Rajesh M. SANKARAN ,  Sanjay K. KUMAR ,  Utkarsh Y. KAKAIYA ,  Philip LANTZ ,  Kun TIAN

IPC: G06F9/455 ,  G06F13/42

Abstract: Examples may include a method of instantiating a virtual machine, instantiating a virtual device to transmit data to and receive data from assigned resources of a shared physical device; and assigning the virtual device to the virtual machine, the virtual machine to transmit data to and receive data from the physical device via the virtual device.

公开(公告)号：US20190114194A1

公开(公告)日：2019-04-18

申请号：US16211934

申请日：2018-12-06

Applicant: Intel Corporation

Inventor： Nrupal JANI ,  Manasi DEVAL ,  Anjali SINGHAI ,  Parthasarathy SARANGAM ,  Mitu AGGARWAL ,  Neerav PARIKH ,  Alexander H. DUYCK ,  Kiran PATIL ,  Rajesh M. SANKARAN ,  Sanjay K. KUMAR ,  Utkarsh Y. KAKAIYA ,  Philip LANTZ ,  Kun TIAN

IPC: G06F9/455

Abstract: Examples may include a method of instantiating a virtual machine; instantiating a virtual device to transmit data to and receive data from assigned resources of a shared physical device by receiving input data requesting assigned resources for the virtual device, allocating assigned resources to the virtual device based at least in part on the input data, and mapping a page location in an address space of the shared physical device for a selected one of the assigned resources to a page location in a memory-mapped input/output (MMIO) space of the virtual device; and assigning the virtual device to the virtual machine, the virtual machine to transmit data to and receive data from the physical device via the MMIO space of the virtual device.

公开(公告)号：US20190108106A1

公开(公告)日：2019-04-11

申请号：US16211955

申请日：2018-12-06

Applicant: Intel Corporation

Inventor： Mitu AGGARWAL ,  Nrupal JANI ,  Manasi DEVAL ,  Kiran PATIL ,  Parthasarathy SARANGAM ,  Rajesh M. SANKARAN ,  Sanjay K. KUMAR ,  Utkarsh Y. KAKAIYA ,  Philip LANTZ ,  Kun TIAN

IPC: G06F11/20 ,  G06F13/40 ,  G06F15/173

Abstract: Examples include a method of performing failover of in an I/O architecture by allocating a first set of resources, associated with a first port of a physical device, to a virtual device, allocating a second set of resources, associated with a second port of the physical device, to the virtual device, assigning the virtual device to a virtual machine, activating the first set of resources, and transferring data between the virtual machine and the first port using the virtual device and the first set of resources. The method further includes detecting an error in the first set of resources, deactivating the first set of resources and activating the second set of resources, and transferring data between the virtual machine and the second port using the virtual device and the second set of resources.

公开(公告)号：US20180373570A1

公开(公告)日：2018-12-27

申请号：US16062568

申请日：2015-12-22

Applicant: INTEL CORPORATION

Inventor： Jiajun XU ,  Kun TIAN ,  Zhiyuan LV ,  Xiaowei WANG

IPC: G06F9/50 ,  G06T1/20 ,  G06F9/455

Abstract: An apparatus and method are described for intelligent cloud based testing of graphics hardware and software. For example, one embodiment of an apparatus comprises: a hardware pool comprising a plurality of test machines to perform cloud-based graphics validation operations; a virtual resource pool comprising data associated a plurality of different graphics hardware resources; a resource manager to coordinate between the hardware pool and the virtual resource pool to cause one or more virtual machines (VMs) to be executed on one or more of the test machines using resources from the virtual resource pool; and a task dispatcher to dispatch graphics validation tasks to the VMs responsive to user input.

公开(公告)号：US20250117264A1

公开(公告)日：2025-04-10

申请号：US18935248

申请日：2024-11-01

Applicant: Intel Corporation

Inventor： Utkarsh Y. KAKAIYA ,  Rajesh M. SANKARAN ,  Sanjay KUMAR ,  Kun TIAN ,  Philip LANTZ

IPC: G06F9/54 ,  G06F9/455 ,  G06F9/48 ,  G06F15/17

Abstract: Techniques for scalable virtualization of an Input/Output (I/O) device are described. An electronic device composes a virtual device comprising one or more assignable interface (AI) instances of a plurality of AI instances of a hosting function exposed by the I/O device. The electronic device emulates device resources of the I/O device via the virtual device. The electronic device intercepts a request from the guest pertaining to the virtual device, and determines whether the request from the guest is a fast-path operation to be passed directly to one of the one or more AI instances of the I/O device or a slow-path operation that is to be at least partially serviced via software executed by the electronic device. For a slow-path operation, the electronic device services the request at least partially via the software executed by the electronic device.

公开(公告)号：US20220197805A1

公开(公告)日：2022-06-23

申请号：US17479954

申请日：2021-09-20

Applicant: Intel Corporation

Inventor： Shaopeng HE ,  Anjali Singhai JAIN ,  Patrick MALONEY ,  Yadong LI ,  Chih-Jen CHANG ,  Kun TIAN ,  Yan ZHAO ,  Rajesh M. SANKARAN ,  Ashok RAJ

IPC: G06F12/0831 ,  G06F12/1009 ,  G06F9/455

Abstract: Examples described herein relate to at least one processor and circuitry, when operational, to: in connection with a request from a device to copy data to a destination memory address: based on a page fault, copy the data to a backup page and after determination of a virtual-to-physical address translation, copy the data from the backup page to a destination page identified by the physical address. In some examples, the copy the data to a backup page is based on a page fault and an indication that a target buffer for the data is at or above a threshold level of fullness. In some examples, copying the data to a backup page includes: receive the physical address of the backup page from the device and copy data from the device to the backup page based on identification of the backup page.

公开(公告)号：US20220107910A1

公开(公告)日：2022-04-07

申请号：US17550977

申请日：2021-12-14

Applicant: Intel Corporation

Inventor： Sanjay KUMAR ,  Rajesh M. SANKARAN ,  Philip R. LANTZ ,  Utkarsh Y. KAKAIYA ,  Kun TIAN

IPC: G06F13/24 ,  G06F9/455 ,  G06F9/48

Abstract: Implementations of the disclosure provide processing device comprising: an interrupt managing circuit to receive an interrupt message directed to an application container from an assignable interface (AI) of an input/output (I/O) device. The interrupt message comprises an address space identifier (ASID), an interrupt handle and a flag to distinguish the interrupt message from a direct memory access (DMA) message. Responsive to receiving the interrupt message, a data structure associated with the interrupt managing circuit is identified. An interrupt entry from the data structure is selected based on the interrupt handle. It is determined that the ASID associated with the interrupt message matches an ASID in the interrupt entry. Thereupon, an interrupt in the interrupt entry is forwarded to the application container.

公开(公告)号：US20210035348A1

公开(公告)日：2021-02-04

申请号：US17072253

申请日：2020-10-16

Applicant: INTEL CORPORATION

Inventor： Prasoonkumar SURTI ,  Tomas G. AKENINE-MOLLER ,  David J. COWPERTHWAITE ,  Kun TIAN ,  Peter L. DOYLE ,  Brent E. INSKO ,  Adam T. LAKE

IPC: G06T15/00 ,  G06T1/20 ,  G06T1/60 ,  G06T15/40 ,  G06T15/50

Abstract: A virtual reality apparatus and method are described for tile-based rendering. For example, one embodiment of an apparatus comprises: a set of on-chip geometry buffers including a first buffer to store geometry data, and a set of pointer buffers to store pointers to the geometry data; a tile-based immediate mode rendering (TBIMR) module to perform tile-based immediate mode rendering using geometry data and pointers stored within the set of on-chip geometry buffers; spill circuitry to determine when the on-chip geometry buffers are over-subscribed and responsively spill additional geometry data and/or pointers to an off-chip memory; and a prefetcher to start prefetching the geometry data from the off-chip memory as space becomes available within the on-chip geometry buffers, the TBIMR module to perform tile-based immediate mode rendering using the geometry data prefetched from the off-chip memory.