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公开(公告)号：US12132457B2
公开(公告)日：2024-10-29
申请号：US17131824
申请日：2020-12-23
Applicant: Intel Corporation
Inventor： Martin Clara , Giacomo Cascio
CPC classification number: H03F3/45192 , H03F1/303 , H03F2200/153
Abstract: A buffer circuit is provided. The buffer circuit includes a Current Differencing Transconductance Amplifier (CDTA) comprising a first input node and a second input node each configured to receive a respective one of a first signal and a second signal. The buffer circuit further includes a first source follower circuit coupled to a first output node of the CDTA and configured to generate a first buffer output signal based on a first output signal of the CDTA. Additionally, the buffer circuit includes a second source follower circuit coupled to a second output node of the CDTA and configured to generate a second buffer output signal based on a second output signal of the CDTA. The buffer circuit further includes a first feedback path comprising at least one of a first resistive element and a first capacitive element. The first feedback path couples an output node of the first source follower circuit to the first input node of the CDTA. In addition, the buffer circuit includes a second feedback path comprising at least one of a second resistive element and a second capacitive element. The second feedback path couples an output node of the second source follower circuit to the second input node of the CDTA.
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22.发明授权公开(公告)号：US12113500B2
公开(公告)日：2024-10-08
申请号：US17131809
申请日：2020-12-23
Applicant: Intel Corporation
Inventor： Daniel Gruber , L Mark Elzinga , Martin Clara , Giacomo Cascio
CPC classification number: H03H11/24 , H04B1/1607 , H04W88/08
Abstract: An attenuator circuit is provided. The attenuator circuit includes a first input node and a second input node each configured to receive a respective one of a first input signal and a second input signal forming a differential input signal pair. Further, the attenuator circuit includes a first plurality of resistive elements coupled in series between the first input node and a first output node for outputting a first output signal. The attenuator circuit additionally includes a second plurality of resistive elements coupled in series between the second input node and a second output node for outputting a second output signal. In addition, the attenuator circuit includes a shunt path coupled to a first intermediate node and a second intermediate node. The first intermedia node is arranged between two resistive elements of the first plurality of resistive elements. The second intermedia node is arranged between two resistive elements of the second plurality of resistive elements. The shunt path comprises a switch circuit configured to selectively couple the first intermediate node and the second intermediate node based on one or more control signals.
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公开(公告)号：US12034450B2
公开(公告)日：2024-07-09
申请号：US17754308
申请日：2019-12-27
Applicant: Intel Corporation
Inventor： Daniel Gruber , Ramon Sanchez , Kameran Azadet , Martin Clara
CPC classification number: H03M1/1033 , H03M1/0626
Abstract: An apparatus for correcting a mismatch between a first segment and a second segment of a Digital-to-Analog Converter, DAC, is provided. The first segment generates a first contribution to an analog output signal of the DAC based on a first number of bits of a digital input word for the DAC converter, and the second segment generates a second contribution based on a second number of bits. Further, the apparatus comprises a first processing circuit for the first number of bits comprising a first filter configured to modify the first number of bits to generate first modified bits, and a second processing circuit comprising a second filter to modify the second number of bits to generate second modified bits. The apparatus additionally comprises an output configured to output a modified digital input word for the DAC, which is based on the first modified bits and the second modified bits.
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公开(公告)号：US12028090B2
公开(公告)日：2024-07-02
申请号：US17754310
申请日：2019-12-23
Applicant: Intel Corporation
Inventor： Albert Molina , Kameran Azadet , Martin Clara , Hundo Shin
CPC classification number: H03M1/808
Abstract: A digital-to-analog converter is provided. The digital-to-analog converter includes a delay circuit configured to iteratively delay a digital input signal based on a clock signal for generating a plurality of delayed digital input signals. Further, the digital-to-analog converter includes a plurality of groups of inverter cells. Each group of inverter cells is configured to generate a respective analog signal based on one of the plurality of delayed digital input signals. The inverter cells includes a respective inverter circuit configured to invert the respective delayed digital input signal. The plurality of groups of inverter cells include different numbers of inverter cells. The digital-to-analog converter additionally includes an output configured to output an analog output signal based on the analog signals of the plurality of groups of inverter cells.
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公开(公告)号：US12015417B2
公开(公告)日：2024-06-18
申请号：US17131868
申请日：2020-12-23
Applicant: Intel Corporation
Inventor： Daniel Gruber , Matteo Camponeschi , Christian Lindholm , Martin Clara , Giacomo Cascio
CPC classification number: H03M1/0609 , H03K3/02 , H04B1/16
Abstract: An input buffer circuit for an analog-to-digital converter is provided. The input buffer circuit includes a buffer amplifier. The buffer amplifier includes a first input node and a second input node each configured to receive a respective one of a first input signal and a second input signal forming a differential input signal pair for the analog-to-digital converter. The buffer amplifier further includes a first output node and a second output node each configured to output a respective one of a first buffered signal and a second buffered signal. In addition, the input buffer circuit includes feedback circuitry. The feedback circuitry is configured to generate, based on the first buffered signal and the second buffered signal, a first feedback signal and a second feedback signal for mitigating a respective unwanted signal component at the first input node and the second input node related to a limited reverse isolation of the amplifier buffer. The feedback circuitry is further configured to supply the first feedback signal to the first input node and the second feedback signal to the second input node.
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Patent Agency Ranking
公开(公告)号：US11901908B2
公开(公告)日：2024-02-13
申请号：US17754148
申请日：2019-12-23
Applicant: Intel Corporation
Inventor： Daniel Gruber , Kameran Azadet , Yu-Shan Wang , Hundo Shin , Martin Clara
CPC classification number: H03M1/0614 , H04B1/0475 , H04B1/1018
Abstract: A Digital-to-Analog Converter, DAC, is provided. The DAC comprises one or more first DAC cells configured to generate a first analog signal based on first digital data. The one or more first DAC cells are coupled to a first output node for coupling to a first load. The DAC comprises one or more second DAC cells configured to generate a second analog signal based on second digital data. The one or more second DAC cells are coupled to a second output node for coupling to a second load. The one or more first DAC cells and the one or more second DAC cells are couplable to a power supply for drawing a supply current. The DAC further comprises a data generation circuit configured to generate the second digital data based on the first digital data.
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公开(公告)号：US11637560B2
公开(公告)日：2023-04-25
申请号：US17455221
申请日：2021-11-17
Applicant: Intel Corporation
Inventor： Martin Clara , Daniel Gruber , Kameran Azadet
Abstract: A segmented digital-to-analog converter (DAC) includes DAC segments, an overrange DAC, and a dither control circuit. Each DAC segment includes a plurality of DAC cells for generating an analog output signal based on input data to each DAC segment. The overrange DAC generates an analog output signal based on a control signal. The dither control circuit adds a dither to first input data supplied to a higher-order DAC segment, subtract a portion of the dither from second input data supplied to a lower-order DAC segment, and generate the control signal for subtracting a remaining portion of the dither from an output of the segmented DAC in an analog domain. The dither added to the first input data may be one of +1, 0, and −1 and the portion of the dither subtracted from the second input data may be a half of the dither added to the first input data.
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公开(公告)号：US11601121B2
公开(公告)日：2023-03-07
申请号：US16912800
申请日：2020-06-26
Applicant: Intel Corporation
Inventor： Giacomo Cascio , Martin Clara , Christian Lindholm
IPC: H03K17/041 , G11C27/02 , H03F3/45 , H03M1/12 , H04B1/40
Abstract: The present disclosure relates to a bootstrapped switch circuit, a track-and-hold circuit, an analog-to-digital converter, a method for operating a track-and-hold circuit, a base station, and a mobile station. The bootstrapped switch circuit comprises an output for an output signal, a first input, a switching element configured to couple the output with a signal from the first input, a bootstrapper capacitor configured to drive the switching element, and a second input coupled to the bootstrapper capacitor.
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29.发明授权公开(公告)号：US11378999B2
公开(公告)日：2022-07-05
申请号：US16724486
申请日：2019-12-23
Applicant: Intel Corporation
Inventor： Yu-Shan Wang , Martin Clara , Daniel Gruber , Hundo Shin , Kameran Azadet
Abstract: An apparatus for generating synchronized clock signals is provided. The apparatus comprises a first circuit comprising a clock divider circuit configured to receive a first clock signal and to generate a second clock signal by frequency dividing the first clock signal. Further, the apparatus comprises a one or more second circuits comprising a respective synchronization circuit configured to receive the first clock signal. The synchronization circuit of one of the one or more second circuits is configured to receive the second clock signal from the first circuit and to resample the second clock signal based on the first clock signal in order to generate a replica of the second clock signal that is in phase with the second clock signal.
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公开(公告)号：US11239866B2
公开(公告)日：2022-02-01
申请号：US16924274
申请日：2020-07-09
Applicant: Intel Corporation
Inventor： Daniel Gruber , Ramon Sanchez , Kameran Azadet , Martin Clara
Abstract: A digital-to-analog conversion system is provided. The digital-to-analog conversion system includes a digital-to-analog converter configured to receive a pre-distorted digital signal from a digital circuit, and to generate an analog signal based on the pre-distorted digital signal. Further, the digital-to-analog conversion system includes a feedback loop for providing a digital feedback signal to the digital circuit. The feedback loop includes an analog-to-digital converter configured to generate the digital feedback signal based on the analog signal, and wherein a sample rate of the analog-to-digital converter is lower than a sample rate of the digital-to-analog converter.
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