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公开(公告)号：US10658056B2
公开(公告)日：2020-05-19
申请号：US15852785
申请日：2017-12-22
Applicant: Intel Corporation
Inventor： Shankar Natarajan , Wayne Tran
Abstract: An embodiment of a semiconductor package apparatus may include technology to attempt to program data in a first portion of a nonvolatile memory, determine if the attempt was successful, and recover the data to a second portion of the nonvolatile memory with an internal data move operation if the attempt is determined to be not successful. Other embodiments are disclosed and claimed.
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公开(公告)号：US10430108B2
公开(公告)日：2019-10-01
申请号：US15721483
申请日：2017-09-29
Applicant: INTEL CORPORATION
Inventor： Shankar Natarajan , Aliasgar S. Madraswala
Abstract: A determination is made that data has to be moved internally within a non-volatile memory from a plurality of pages of a first type of storage media to a page of a second type of storage media. A first subset of the plurality of pages is copied from the first type of storage media to the page of the second type of storage media. Concurrently with the copying of the first subset of the plurality of pages, a second subset of the plurality of pages is copied from the first type of storage media to the page of the second type of storage media. In response to completion of the copying of the first subset and the second subset of the plurality of pages, it is determined that the copying of the data from the first type of storage media to the second type of storage media has completed.
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公开(公告)号：US20190180830A1
公开(公告)日：2019-06-13
申请号：US15852785
申请日：2017-12-22
Applicant: Intel Corporation
Inventor： Shankar Natarajan , Wayne Tran
Abstract: An embodiment of a semiconductor package apparatus may include technology to attempt to program data in a first portion of a nonvolatile memory, determine if the attempt was successful, and recover the data to a second portion of the nonvolatile memory with an internal data move operation if the attempt is determined to be not successful. Other embodiments are disclosed and claimed.
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公开(公告)号：US10229735B1
公开(公告)日：2019-03-12
申请号：US15852928
申请日：2017-12-22
Applicant: Intel Corporation
Inventor： Shankar Natarajan , Sriram Natarajan , Suresh Nagarajan , Ramkarthik Ganesan , Arun S. Athreya , Romesh B. Trivedi
Abstract: Systems, apparatuses and methods may provide for technology to determine a programmable eviction ratio associated with a storage device and convert a portion of a single-level cell region in the storage device into a multi-level cell region in accordance with the programmable eviction ratio. In one example, the amount of the portion converted into the multi-level cell region varies gradually as a function of percent capacity filled in the storage device.
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25.发明申请公开(公告)号：US20190041947A1
公开(公告)日：2019-02-07
申请号：US16022675
申请日：2018-06-28
Applicant: Intel Corporation
Inventor： Shankar Natarajan , Wayne Tran , Vishal Mannapur , Anthony Giardina
Abstract: Technologies for dynamically managing a power state of a first endpoint device and a second endpoint device that are operatively coupled to a data bus of a compute device include communication monitor circuitry and power state manager circuitry. The communication monitor circuitry is configured to detect an activation signal on the data bus. The power state manager circuitry is configured to activate, in response to detection of the activation signal, the first and second endpoint devices that are operatively coupled to the data bus into a high power state from a low power state, determine, in response to activation of the first and second endpoint devices, which activated endpoint device is requested to perform work associated with the activation signal, and operate, in response to determination that the second endpoint device has no pending work to perform, the second endpoint device to return to the low power state.
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Patent Agency Ranking
公开(公告)号：US11302405B2
公开(公告)日：2022-04-12
申请号：US16709749
申请日：2019-12-10
Applicant: Intel Corporation
Inventor： Sriram Natarajan , Shankar Natarajan , Yihua Zhang , Hinesh K. Shah , Rohit S. Shenoy , Arun Sitaram Athreya
Abstract: A nonvolatile (NV) memory device includes an NV storage media and a storage controller to control access to the NV storage media. In response to a host read request, the storage controller can determine if the NV storage media is in a stable Vt (threshold voltage) state. If the NV storage media is in a stable Vt state, the storage controller can perform a reset read operation prior to servicing the host read request. A reset read is a read operation that does not produce data to send back to the host. The reset read operation is a dummy read that puts the NV storage media into a transient Vt state, which has lower risk of read disturb.
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公开(公告)号：US11145389B2
公开(公告)日：2021-10-12
申请号：US16702290
申请日：2019-12-03
Applicant: Intel Corporation
Inventor： Shankar Natarajan , Sriram Natarajan , Arun S. Athreya , Venkata S. Surampudi
Abstract: An embodiment of an electronic apparatus may include one or more substrates, and logic coupled to the one or more substrates, the logic to control a persistent storage media including a first media to store one or more source blocks of data and a second media to store one or more destination blocks of data, determine if an error rate associated with a read of a particular destination block of the one or more destination blocks exceeds a threshold error rate, identify a particular source block of the one or more source blocks which corresponds to erroneous data in the particular destination block, determine which of the particular source block and the particular destination block is a failed block, and retire the failed block. Other embodiments are disclosed and claimed.
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28.发明授权公开(公告)号：US10909040B2
公开(公告)日：2021-02-02
申请号：US15957650
申请日：2018-04-19
Applicant: Intel Corporation
Inventor： Shankar Natarajan , Romesh Trivedi
IPC: G06F12/08 , G06F12/0871 , G06F12/02 , G06F12/0891
Abstract: A solid state drive (SSD) includes different segments of nonvolatile (NV) storage media with different access times. The NV media segment with faster access time operates as a cache for the segment with the slower access time. The SSD implements idle eviction from the cache segment to the other segment based on an idle condition of the SSD. The SSD can dynamically change application of the idle eviction based on a power management state indicated for the hardware platform. Thus, a change in power management state of the hardware platform associated with the SSD can cause the SSD to implement idle eviction differently.
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公开(公告)号：US10650886B2
公开(公告)日：2020-05-12
申请号：US16288268
申请日：2019-02-28
Applicant: Intel Corporation
Inventor： Shankar Natarajan , Sriram Natarajan , Suresh Nagarajan , Ramkarthik Ganesan , Arun S. Athreya , Romesh B. Trivedi
Abstract: Systems, apparatuses and methods may provide for technology to determine a programmable eviction ratio associated with a storage device and convert a portion of a single-level cell region in the storage device into a multi-level cell region in accordance with the programmable eviction ratio. In one example, the amount of the portion converted into the multi-level cell region varies gradually as a function of percent capacity filled in the storage device.
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公开(公告)号：US10395728B2
公开(公告)日：2019-08-27
申请号：US16019530
申请日：2018-06-26
Applicant: INTEL CORPORATION
Inventor： Ning Wu , Shankar Natarajan
Abstract: A non-volatile memory receives a request from a controller to read data stored in the memory. Moving read references are adjusted as a function of the temperature of the memory at which the data was written and the temperature of the memory at which the data is to be read. Moving read references may also be adjusted as a function of the retention time of the data to be read and the word line type of the storage elements in which the data is stored.
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