公开(公告)号：US09946875B2

公开(公告)日：2018-04-17

申请号：US15398930

申请日：2017-01-05

Applicant: Intel Corporation

Inventor： Stephen A. Fischer ,  Kevin C. Gotze ,  Yuriy Bulygin ,  Kirk D. Brannock

IPC: G06F21/50 ,  G06F21/55 ,  G06F21/56 ,  G06F9/30

CPC classification number: G06F21/552 ,  G06F9/30145 ,  G06F21/566 ,  G06F2221/034

Abstract: In one embodiment, a processor includes at least one execution unit and Return Oriented Programming (ROP) detection logic. The ROP detection logic may determine a ROP metric based on a plurality of control transfer events. The ROP detection logic may also determine whether the ROP metric exceeds a threshold. The ROP detection logic may also, in response to a determination that the ROP metric exceeds the threshold, provide a ROP attack notification.

公开(公告)号：US20180060078A1

公开(公告)日：2018-03-01

申请号：US15672254

申请日：2017-08-08

Applicant: Intel Corporation

Inventor： Eliezer Weissmann ,  Rinat Rappoport ,  Michael Mishaeli ,  Hisham Shafi ,  Oron Lenz ,  Jason W. Brandt ,  Stephen A. Fischer ,  Bret L. Toll ,  Inder M. Sodhi ,  Alon Naveh ,  Ganapati N. Srinivasa ,  Ashish V, Choubal ,  Scott D. Hahn ,  David A. Koufaty ,  Russel J. Fenger ,  Gaurav Khanna ,  Eugene Gorbatov ,  Mishali Naik ,  Andrew J. Herdrich ,  Abirami Prabhakaran ,  Sanjeev S. Sahagirdar ,  Paul Brett ,  Paolo Narvaez ,  Andrew D. Henroid ,  Dheeraj R. Subbareddy

IPC: G06F9/44 ,  G06F9/50 ,  G06F9/455

Abstract: A heterogeneous processor architecture and a method of booting a heterogeneous processor is described. A processor according to one embodiment comprises: a set of large physical processor cores; a set of small physical processor cores having relatively lower performance processing capabilities and relatively lower power usage relative to the large physical processor cores; and a package unit, to enable a bootstrap processor. The bootstrap processor initializes the homogeneous physical processor cores, while the heterogeneous processor presents the appearance of a homogeneous processor to a system firmware interface.

公开(公告)号：US09870044B2

公开(公告)日：2018-01-16

申请号：US15280057

申请日：2016-09-29

Applicant: Intel Corporation

Inventor： Sanjeev Jahagirdar ,  Varghese George ,  John B. Conrad ,  Robert Milstrey ,  Stephen A. Fischer ,  Alon Naveh ,  Shai Rotem

IPC: G06F1/32 ,  G06F12/08 ,  G06F11/14 ,  G06F12/084 ,  G06F12/0875 ,  G11C7/10 ,  G06F9/44

CPC classification number: G06F1/3287 ,  G06F1/3203 ,  G06F1/324 ,  G06F1/3243 ,  G06F1/3246 ,  G06F1/3275 ,  G06F1/3293 ,  G06F1/3296 ,  G06F9/4418 ,  G06F11/1441 ,  G06F12/084 ,  G06F12/0875 ,  G06F2212/281 ,  G06F2212/305 ,  G06F2212/314 ,  G11C7/1072 ,  Y02B70/123 ,  Y02B70/126 ,  Y02B70/32 ,  Y02D10/152 ,  Y02D10/172 ,  Y02D50/20 ,  Y02P80/11 ,  Y10T307/305 ,  Y10T307/406 ,  Y10T307/582 ,  Y10T307/826

Abstract: Embodiments of the invention relate to a method and apparatus for a zero voltage processor sleep state. A processor may include a dedicated cache memory. A voltage regulator may be coupled to the processor to provide an operating voltage to the processor. During a transition to a zero voltage power management state for the processor, the operational voltage applied to the processor by the voltage regulator may be reduced to approximately zero and the state variables associated with the processor may be saved to the dedicated cache memory.

公开(公告)号：US09223979B2

公开(公告)日：2015-12-29

申请号：US13664532

申请日：2012-10-31

Applicant: Intel Corporation

Inventor： Stephen A. Fischer ,  Kevin C. Gotze ,  Yuriy Bulygin ,  Kirk D. Brannock

IPC: G06F21/50 ,  G06F21/56

CPC classification number: G06F21/552 ,  G06F9/30145 ,  G06F21/566 ,  G06F2221/034

Abstract: In one embodiment, a processor includes at least one execution unit and Return Oriented Programming (ROP) detection logic. The ROP detection logic may determine a ROP metric based on a plurality of control transfer events. The ROP detection logic may also determine whether the ROP metric exceeds a threshold. The ROP detection logic may also, in response to a determination that the ROP metric exceeds the threshold, provide a ROP attack notification.

Abstract translation: 在一个实施例中，处理器包括至少一个执行单元和返回定向编程（ROP）检测逻辑。 ROP检测逻辑可以基于多个控制传送事件来确定ROP度量。 ROP检测逻辑还可以确定ROP度量是否超过阈值。 ROP检测逻辑还可以响应于ROP度量超过阈值的确定，提供ROP攻击通知。

公开(公告)号：US09141180B2

公开(公告)日：2015-09-22

申请号：US14630909

申请日：2015-02-25

Applicant: Intel Corporation

Inventor： Sanjeev Jahagirdar ,  Varghese George ,  John Conrad ,  Robert Milstrey ,  Stephen A. Fischer ,  Alon Naveh ,  Shai Rotem

IPC: G06F1/32

CPC classification number: G06F1/3287 ,  G06F1/3203 ,  G06F1/324 ,  G06F1/3243 ,  G06F1/3246 ,  G06F1/3275 ,  G06F1/3293 ,  G06F1/3296 ,  G06F9/4418 ,  G06F11/1441 ,  G06F12/084 ,  G06F12/0875 ,  G06F2212/281 ,  G06F2212/305 ,  G06F2212/314 ,  G11C7/1072 ,  Y02B70/123 ,  Y02B70/126 ,  Y02B70/32 ,  Y02D10/152 ,  Y02D10/172 ,  Y02D50/20 ,  Y02P80/11 ,  Y10T307/305 ,  Y10T307/406 ,  Y10T307/582 ,  Y10T307/826

Abstract: Embodiments of the invention relate to a method and apparatus for a zero voltage processor sleep state. A processor may include a dedicated cache memory. A voltage regulator may be coupled to the processor to provide an operating voltage to the processor. During a transition to a zero voltage power management state for the processor, the operational voltage applied to the processor by the voltage regulator may be reduced to approximately zero and the state variables associated with the processor may be saved to the dedicated cache memory.

Abstract translation: 本发明的实施例涉及一种用于零电压处理器睡眠状态的方法和装置。 处理器可以包括专用高速缓存存储器。 电压调节器可以耦合到处理器以向处理器提供工作电压。 在处理器转换到零电压电源管理状态期间，电压调节器施加到处理器的工作电压可以减小到大约零，并且与处理器相关联的状态变量可以被保存到专用高速缓冲存储器。

公开(公告)号：US20150052377A1

公开(公告)日：2015-02-19

申请号：US14496233

申请日：2014-09-25

Applicant: Intel Corporation

Inventor： Sanjeev Jahagirdar ,  Varghese George ,  John B. Conrad ,  Robert Milstrey ,  Stephen A. Fischer ,  Alon Naveh ,  Shai Rotem

IPC: G06F1/32

CPC classification number: G06F1/3287 ,  G06F1/3203 ,  G06F1/324 ,  G06F1/3243 ,  G06F1/3246 ,  G06F1/3275 ,  G06F1/3293 ,  G06F1/3296 ,  G06F9/4418 ,  G06F11/1441 ,  G06F12/084 ,  G06F12/0875 ,  G06F2212/281 ,  G06F2212/305 ,  G06F2212/314 ,  G11C7/1072 ,  Y02B70/123 ,  Y02B70/126 ,  Y02B70/32 ,  Y02D10/152 ,  Y02D10/172 ,  Y02D50/20 ,  Y02P80/11 ,  Y10T307/305 ,  Y10T307/406 ,  Y10T307/582 ,  Y10T307/826

Abstract: Embodiments of the invention relate to a method and apparatus for a zero voltage processor sleep state. A processor may include a dedicated cache memory. A voltage regulator may be coupled to the processor to provide an operating voltage to the processor. During a transition to a zero voltage power management state for the processor, the operational voltage applied to the processor by the voltage regulator may be reduced to approximately zero and the state variables associated with the processor may be saved to the dedicated cache memory.

Abstract translation: 本发明的实施例涉及一种用于零电压处理器睡眠状态的方法和装置。 处理器可以包括专用高速缓存存储器。 电压调节器可以耦合到处理器以向处理器提供工作电压。 在处理器转换到零电压电源管理状态期间，电压调节器施加到处理器的工作电压可以减小到大约零，并且与处理器相关联的状态变量可以被保存到专用高速缓冲存储器。