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公开(公告)号:US20240006481A1
公开(公告)日:2024-01-04
申请号:US17853547
申请日:2022-06-29
Applicant: Intel Corporation
Inventor: Chelsey DOROW , Kevin P. O'BRIEN , Sudarat LEE , Ande KITAMURA , Ashish Verma PENUMATCHA , Carl H. NAYLOR , Kirby MAXEY , Chia-Ching LIN , Scott B. CLENDENNING , Uygar E. AVCI
IPC: H01L29/06 , H01L29/423 , H01L29/66 , H01L29/786
CPC classification number: H01L29/0673 , H01L29/42392 , H01L29/6681 , H01L29/66545 , H01L29/78696
Abstract: Embodiments disclosed herein include transistors and methods of forming transistors. In an embodiment, the transistor comprises a source region, a drain region, a first semiconductor channel between the source region and the drain region, and a second semiconductor channel between the source region and the drain region over the first semiconductor channel. In an embodiment, an insulator is around the source region, the drain region, the first semiconductor channel, and the second semiconductor channel. In an embodiment, a first access hole is in the insulator adjacent to a first edge of the first semiconductor channel, and a second access hole is in the insulator adjacent to a second edge of the first semiconductor channel.
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公开(公告)号:US20230411278A1
公开(公告)日:2023-12-21
申请号:US18129264
申请日:2023-03-31
Applicant: Intel Corporation
Inventor: Chia-Ching LIN , Sou-Chi CHANG , Kaan OGUZ , Arnab SEN GUPTA , I-Cheng TUNG , Matthew V. METZ , Sudarat LEE , Scott B. CLENDENNING , Uygar E. AVCI , Aaron J. WELSH
IPC: H01L23/522 , H01L27/08
CPC classification number: H01L23/5223 , H01L28/75 , H01L28/91 , H01L27/0805
Abstract: Metal insulator metal capacitors are described. In an example, a metal-insulator-metal (MIM) capacitor includes a first electrode that includes a bottom region and a pair of vertical regions. First metal layers are outside the vertical regions and in contact with the vertical regions. An insulator is over the first electrode. A second electrode is over the insulator. A second metal layer is on a top surface of the second electrode.
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公开(公告)号:US20230317783A1
公开(公告)日:2023-10-05
申请号:US17709365
申请日:2022-03-30
Applicant: Intel Corporation
Inventor: Kirby MAXEY , Carl H. NAYLOR , Uygar E. AVCI , Chelsey DOROW , Kevin P. O'BRIEN , Scott B. CLENDENNING , Matthew V. METZ , Chia-Ching LIN , Sudarat LEE , Ashish Verma PENUMATCHA
IPC: H01L29/06 , H01L29/786 , H01L21/8234 , H01L29/66
CPC classification number: H01L29/0665 , H01L29/78696 , H01L29/66742 , H01L21/823412 , H01L29/78651
Abstract: Embodiments described herein may be related to forming nano ribbon transistors using layered 2D semiconductor channels. The layered 2D semiconductor channels may be created by forming a scaffold structure that has a first edge that extends from a silicon-based substrate, and a second edge opposite the first edge that is distal to the silicon based substrate. Alternating layers of 2D semiconductor material and a 3D semiconductor material may then be built on the second edge of the scaffold structure. In embodiments, the 3D semiconductor material may then be removed and a gate material deposited around at least a portion of the layers of 2D semiconductor material.
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公开(公告)号:US20230098467A1
公开(公告)日:2023-03-30
申请号:US17485176
申请日:2021-09-24
Applicant: Intel Corporation
Inventor: Carl H. NAYLOR , Kirby MAXEY , Kevin P. O'BRIEN , Chelsey DOROW , Sudarat LEE , Ashish Verma PENUMATCHA , Shriram SHIVARAMAN , Uygar E. AVCI , Patrick THEOFANIS , Charles MOKHTARZADEH , Matthew V. METZ , Scott B. CLENDENNING
IPC: H01L27/092 , H01L29/24 , H01L29/06 , H01L29/423 , H01L29/76 , H01L29/786 , H01L21/02 , H01L21/8256 , H01L29/66
Abstract: Thin film transistors having a spin-on two-dimensional (2D) channel material are described. In an example, an integrated circuit structure includes a first device layer including a first two-dimensional (2D) material layer above a substrate. The first 2D material layer includes molybdenum, sulfur, sodium and carbon. A second device layer including a second 2D material layer is above the substrate. The second 2D material layer includes tungsten, selenium, sodium and carbon.
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公开(公告)号:US20230096347A1
公开(公告)日:2023-03-30
申请号:US17485202
申请日:2021-09-24
Applicant: Intel Corporation
Inventor: Kevin P. O'BRIEN , Tristan A. TRONIC , Anandi ROY , Ashish Verma PENUMATCHA , Carl H. NAYLOR , Kirby MAXEY , Sudarat LEE , Chelsey DOROW , Scott B. CLENDENNING , Uygar E. AVCI
IPC: H01L27/092 , H01L29/06 , H01L29/417 , H01L29/423 , H01L29/45 , H01L29/49 , H01L29/786 , H01L21/02 , H01L21/28 , H01L21/8238 , H01L29/66
Abstract: Embodiments disclosed herein include semiconductor devices and methods of forming such devices. In an embodiment, a semiconductor device comprises a sheet that is a semiconductor. In an embodiment a length dimension of the sheet and a width dimension of the sheet are greater than a thickness dimension of the sheet. In an embodiment, a gate structure is around the sheet, and a first spacer is adjacent to a first end of the gate structure, and a second spacer adjacent to a second end of the gate structure. In an embodiment, a source contact is around the sheet and adjacent to the first spacer, and a drain contact is around the sheet and adjacent to the second spacer.
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公开(公告)号:US20230088101A1
公开(公告)日:2023-03-23
申请号:US17482232
申请日:2021-09-22
Applicant: Intel Corporation
Inventor: Carl H. NAYLOR , Kirby MAXEY , Kevin P. O'BRIEN , Chelsey DOROW , Sudarat LEE , Ashish Verma PENUMATCHA , Uygar E. AVCI , Matthew V. METZ , Scott B. CLENDENNING
IPC: H01L29/76 , H01L29/06 , H01L29/24 , H01L29/423 , H01L29/786 , H01L21/02 , H01L29/66
Abstract: Thin film transistors having edge-modulated two-dimensional (2D) channel material are described. In an example, an integrated circuit structure includes a device layer including a two-dimensional (2D) material layer above a substrate, the 2D material layer including a center portion and first and second edge portions, the center portion consisting essentially of molybdenum or tungsten and of sulfur or selenium, and the first and second edge portions including molybdenum or tungsten and including tellurium.
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