公开(公告)号：US20170178708A1

公开(公告)日：2017-06-22

申请号：US15371122

申请日：2016-12-06

Applicant: Intel Corporation

Inventor： Charles AUGUSTINE ,  Shigeki TOMISHIMA ,  Wei WU ,  Shih-Lien LU ,  James W. TSCHANZ ,  Georgios PANAGOPOULOS ,  Helia NAEIMI

IPC: G11C11/16

CPC classification number: G11C11/1675 ,  G11C11/1659 ,  G11C11/1677 ,  G11C11/1693 ,  G11C11/1697

Abstract: An apparatus is described that includes a semiconductor chip memory array having resistive storage cells. The apparatus also includes a comparator to compare a first word to be written into the array against a second word stored in the array at the location targeted by a write operation that will write the first word into the array. The apparatus also includes circuitry to iteratively write to one or more bit locations where a difference exists between the first word and the second word with increasing write current intensity with each successive iteration.

公开(公告)号：US20170126249A1

公开(公告)日：2017-05-04

申请号：US14929163

申请日：2015-10-30

Applicant: INTEL CORPORATION

Inventor： Wei WU ,  Charles AUGUSTINE ,  Shigeki TOMISHIMA ,  Shih-lien L. LU ,  James W. TSCHANZ

IPC: H03M13/05 ,  H03M13/00

CPC classification number: H03M13/05 ,  G06F11/1048 ,  H03M13/1515 ,  H03M13/353 ,  H03M13/611 ,  H03M13/6502 ,  H03M13/6516

Abstract: In one embodiment, temperature dependent, multiple mode error correction in accordance with one aspect of this disclosure, is employed for a memory circuit containing arrays of memory cells. In one embodiment, a temperature sensor coupled to an array is configured to provide an output signal which is a function of the temperature of the array of memory cells. Multiple mode error correction code (ECC) logic having an input coupled to an output of the temperature sensor, is configured to encode write data and decode read data for the array of memory cells in an error correction code in one of a plurality of error correction modes as a function of the temperature of the array of memory cells. Other aspects are described herein.