公开(公告)号：US06376324B1

公开(公告)日：2002-04-23

申请号：US09602969

申请日：2000-06-23

申请人： Jack A. Mandelman ,  Ramachandra Divakaruni ,  Carl J. Radens ,  Ulrike Gruening ,  Akira Sudo

发明人： Jack A. Mandelman ,  Ramachandra Divakaruni ,  Carl J. Radens ,  Ulrike Gruening ,  Akira Sudo

IPC分类号： H01L2120

CPC分类号： H01L27/10867

摘要： Disclosed is a method to provide a new deep trench collar process which reduces encroachment of strap diffusion upon array metal oxide semiconductor field effect transistors (MOSFET's) in semiconductor devices. The invention allows a reduced effective deep trench edge bias at the top of the deep trench, without compromising storage capacitance, by maximizing the distance between the MOSFET gate conductor and the deep trench storage capacitor.

摘要翻译： 公开了一种提供新的深沟槽套环工艺的方法，其减少了半导体器件中的阵列金属氧化物半导体场效应晶体管（MOSFET）上带扩散的侵入。 通过使MOSFET栅极导体和深沟槽存储电容器之间的距离最大化，本发明允许在深沟槽顶部减少有效的深沟槽边缘偏压，而不损害存储电容。

公开(公告)号：US06348374B1

公开(公告)日：2002-02-19

申请号：US09597887

申请日：2000-06-19

申请人： Satish D. Athavale ,  Gary B. Bronner ,  Ramachandra Divakaruni ,  Ulrike Gruening ,  Jack A. Mandelman ,  Carl J. Radens

发明人： Satish D. Athavale ,  Gary B. Bronner ,  Ramachandra Divakaruni ,  Ulrike Gruening ,  Jack A. Mandelman ,  Carl J. Radens

IPC分类号： H01L218242

CPC分类号： H01L27/10876 ,  H01L27/10814 ,  H01L27/10823 ,  H01L27/10885

摘要： A method of forming a vertical transistor. A pad layer is formed over a semiconductor substrate. A trough is formed through the pad layer and in the semiconductor substrate. A bit line is formed buried in the trough. The bit line is enclosed by a dielectric material. A strap is formed extending through the dielectric material to connect the bit line to the semiconductor substrate. The trough is filled above the bit line with a conductor. The conductor is cut along its longitudinal axis such that the conductor remains on one side of the trough. Wordline troughs are formed, substantially orthogonal to the bit line, above the semiconductor substrate. A portion of the conductor is removed under the wordline trough to separate the conductor into separate gate conductors. Wordlines are formed in the wordline trough connected to the separate gate conductors.

摘要翻译： 一种形成垂直晶体管的方法。 在半导体衬底上形成衬垫层。 通过焊盘层和半导体衬底形成槽。 埋在槽中的位线形成。 位线被电介质材料包围。 形成延伸穿过介电材料的带，以将位线连接到半导体衬底。 槽被填充在位线上方的导体。 导体沿其纵向轴线切割，使得导体保持在槽的一侧。 在半导体衬底之上形成基本上与位线正交的字线槽。 导体的一部分在字线槽下移除，以将导体分离成单独的栅极导体。 字线形成在连接到单独的栅极导体的字线槽中。

公开(公告)号：US06150212A

公开(公告)日：2000-11-21

申请号：US359287

申请日：1999-07-22

申请人： Ramachandra Divakaruni ,  Jeffrey P. Gambino ,  Jack A. Mandelman ,  Carl J. Radens ,  William R. Tonti

发明人： Ramachandra Divakaruni ,  Jeffrey P. Gambino ,  Jack A. Mandelman ,  Carl J. Radens ,  William R. Tonti

IPC分类号： H01L21/762 ,  H01L21/8242

CPC分类号： H01L21/76232 ,  H01L27/10861 ,  H01L27/1087

摘要： A method for forming an isolation trench region in a semiconductor substrate includes providing the trench region in the semiconductor substrate, adding spacer material at least to sidewalls of the trench region, and etching the trench region at a bottom surface thereof to extend the trench region below the bottom surface and form a crevice region. The spacer material may be subsequently heated such that the spacer material flows from the sidewalls and into the crevice region.

摘要翻译： 一种用于在半导体衬底中形成隔离沟槽区域的方法包括：在半导体衬底中设置沟槽区域，至少在沟槽区域的侧壁上添加衬垫材料，并在其底表面处蚀刻沟槽区域，以将沟槽区域延伸到下面 底面并形成缝隙区域。 间隔物材料可以随后被加热，使得间隔物材料从侧壁流入缝隙区域。

公开(公告)号：US06808981B2

公开(公告)日：2004-10-26

申请号：US10375654

申请日：2003-02-27

申请人： Jack A. Mandelman ,  Ramachandra Divakaruni ,  Carl J. Radens ,  Gary B. Bronner

发明人： Jack A. Mandelman ,  Ramachandra Divakaruni ,  Carl J. Radens ,  Gary B. Bronner

IPC分类号： H01L218242

CPC分类号： H01L27/10864 ,  H01L21/823481 ,  H01L21/823487

摘要： A memory cell containing double-gated vertical metal oxide semiconductor field effect transistors (MOSFETs) and isolation regions such as shallow trench isolation, STI, regions that are self-aligned to the wordlines and bitlines of the cell are provided. The inventive memory cell substantially eliminates the backgating problem and floating well effects that are typically present in prior art memory cells. A method of fabricating the inventive memory cell is also provided.

摘要翻译： 提供了包含双门控垂直金属氧化物半导体场效应晶体管（MOSFET）和隔离区域（诸如浅沟槽隔离，STI，与单元的字线和位线自对准的区域）的存储单元。 本发明的存储单元基本上消除了现有技术的存储单元中通常存在的背景问题和漂浮阱效应。 还提供了制造本发明的存储单元的方法。

公开(公告)号：US06570208B2

公开(公告)日：2003-05-27

申请号：US09766013

申请日：2001-01-18

申请人： Jack A. Mandelman ,  Ramachandra Divakaruni ,  Carl J. Radens ,  Gary B. Bronner

发明人： Jack A. Mandelman ,  Ramachandra Divakaruni ,  Carl J. Radens ,  Gary B. Bronner

IPC分类号： H01L218242

CPC分类号： H01L27/10864 ,  H01L21/823481 ,  H01L21/823487

摘要： A memory cell containing double-gated vertical metal oxide semiconductor field effect transistors (MOSFETs) and isolation regions such as shallow trench isolation, STI, regions that are self-aligned to the wordlines and bitlines of the cell are provided. The inventive memory cell substantially eliminates the backgating problem and floating well effects that are typically present in prior art memory cells. A method of fabricating the inventive memory cell is also provided.

摘要翻译： 提供了包含双门控垂直金属氧化物半导体场效应晶体管（MOSFET）和隔离区域（诸如浅沟槽隔离，STI，与电池的字线和位线自对准的区域）的存储单元。 本发明的存储单元基本上消除了现有技术的存储单元中通常存在的背景问题和漂浮阱效应。 还提供了制造本发明的存储单元的方法。

公开(公告)号：US06501117B1

公开(公告)日：2002-12-31

申请号：US10007846

申请日：2001-11-05

申请人： Carl J. Radens ,  Gary B. Bronner ,  Ramachandra Divakaruni ,  Jack A. Mandelman

发明人： Carl J. Radens ,  Gary B. Bronner ,  Ramachandra Divakaruni ,  Jack A. Mandelman

IPC分类号： H01L27108

CPC分类号： H01L27/11 ,  G11C11/404 ,  H01L27/10841 ,  H01L27/10864 ,  H01L27/10867 ,  H01L29/945

摘要： A DRAM cell storage capacitor is formed above the bottom of a deep trench (DT) below an FET transistor. The DT has upper, central and lower portions with sidewalls. A capacitor plate electrode, surrounding the lower DT portion that is doped with a first dopant type, is separated by an interface from a well region surrounding the upper and central portions of the DT that are doped with an opposite dopant type. A source/drain region formed at the top of the cell is doped with the first dopant type. A node dielectric layer that covers the sidewalls and bottom of the lower and central portions of the DT is filled with a node electrode of the capacitor, doped with the first dopant type, fills the space inside the node dielectric layer in the lower part of the DT. Above a recessed node dielectric layer a strap region space is filled with a buried-strap conductor. An oxide (TTO) layer is formed over the node electrode and the buried-strap in the DT. A peripheral gate oxide layer, which coats sidewalls of the DT above the TTO, defines a space which is filled with the FET gate electrode. An outdiffusion region, doped with the first dopant type, is formed in the well region near the buried-strap. The cell has a first state and an opposite state of operation. A punch-through device, formed in the well between the outdiffusion region and the interface, provides a self-refreshing punchthrough current in the cell between the well and the plate in the first state of cell operation. A reverse bias junction leakage current occurs in the cell between the buried-strap and the P-well to refresh the opposite state of cell operation.

摘要翻译： 在FET晶体管下方的深沟槽（DT）的底部形成DRAM单元存储电容器。 DT具有具有侧壁的上部，中部和下部。 围绕掺杂有第一掺杂剂类型的下部DT部分的电容器平板电极通过界面与围绕掺杂有相反掺杂剂类型的DT的上部和中部的阱区隔开。 形成在电池顶部的源极/漏极区掺杂有第一掺杂剂类型。 覆盖DT的下部和中心部分的侧壁和底部的节点电介质层填充有掺杂有第一掺杂剂类型的电容器的节点电极，填充第一掺杂剂类型的下部的节点电介质层内部的空间 DT。 在凹陷节点电介质层上方，带区域空间填充有埋地导体。 在DT上的节点电极和掩埋带上形成氧化物（TTO）层。 在TTO上方覆盖DT的侧壁的外围栅极氧化物层限定了用FET栅电极填充的空间。 在掩埋带附近的阱区中形成掺杂有第一掺杂剂类型的扩散区。 电池具有第一状态和相反的操作状态。 形成在扩散区域和界面之间的井中的穿通装置在电池操作的第一状态下在孔和板之间的电池单元中提供自刷新穿透电流。 在埋层和P阱之间的电池中产生反向偏置结漏电流，以刷新电池操作的相反状态。

公开(公告)号：US06284593B1

公开(公告)日：2001-09-04

申请号：US09705652

申请日：2000-11-03

申请人： Jack A. Mandelman ,  Ramachandra Divakaruni ,  Carl J. Radens

发明人： Jack A. Mandelman ,  Ramachandra Divakaruni ,  Carl J. Radens

IPC分类号： H01L218242

CPC分类号： H01L27/10864 ,  H01L27/10867

摘要： A process of forming a hybrid memory cell which is scalable to a minimum feature size, F, of about 60 nm at an operating voltage of Vblh of about 1.5 V and substantially free of floating-well effects is provided.

摘要翻译： 提供了形成混合存储器单元的过程，该混合存储器单元在约1.5V的Vblh的工作电压下可扩展到约60nm的最小特征尺寸F，并且基本上没有浮动阱效应。

公开(公告)号：US07759188B2

公开(公告)日：2010-07-20

申请号：US12002828

申请日：2007-12-19

申请人： Kangguo Cheng ,  Gary B. Bronner ,  Ramachandra Divakaruni ,  Carl J. Radens

发明人： Kangguo Cheng ,  Gary B. Bronner ,  Ramachandra Divakaruni ,  Carl J. Radens

IPC分类号： H01L21/8242

CPC分类号： H01L27/1203 ,  H01L21/84 ,  H01L29/66666 ,  H01L29/78642

摘要： A method of fabricating a vertical field effect transistor (“FET”) is provided which includes a transistor body region and source and drain regions disposed in a single-crystal semiconductor-on-insulator (“SOI”) region of a substrate adjacent a sidewall of a trench. The substrate includes a buried insulator layer underlying the SOI region and a bulk region underlying the buried insulator layer. A buried strap conductively connects the SOI region to a lower node disposed below the SOI region and a body contact extends from the transistor body region to the bulk region of the substrate, the body contact being insulated from the buried strap.

摘要翻译： 提供一种制造垂直场效应晶体管（“FET”）的方法，其包括晶体管本体区域和设置在邻近侧壁的衬底的单晶半导体绝缘体（“SOI”）区域中的源极和漏极区域 的沟渠 衬底包括在SOI区域下面的掩埋绝缘体层和埋在掩埋绝缘体层下面的主体区域。 掩埋带导电地将SOI区域连接到设置在SOI区域下方的下部节点，并且主体接触从晶体管本体区域延伸到衬底的主体区域，身体接触部与掩埋带绝缘。

公开(公告)号：US07737482B2

公开(公告)日：2010-06-15

申请号：US11538982

申请日：2006-10-05

申请人： Kangguo Cheng ,  Ramachandra Divakaruni ,  Carl J. Radens

发明人： Kangguo Cheng ,  Ramachandra Divakaruni ,  Carl J. Radens

IPC分类号： H01L29/76

CPC分类号： H01L27/1203 ,  H01L21/743 ,  H01L21/84 ,  H01L27/10829 ,  H01L27/10867 ,  H01L27/1087 ,  H01L27/1207 ,  H01L29/78

摘要： Structures including a self-aligned strap for embedded trench memory (e.g., trench capacitor) on hybrid orientation technology (HOT) substrate, and related method, are disclosed. One structure includes a hybrid orientation substrate including a semiconductor-on-insulator (SOI) section and a bulk semiconductor section; a transistor over the SOI section; a trench capacitor in the bulk semiconductor section; and a self-aligned strap extending from a source/drain region of the transistor to an electrode of the trench capacitor. The method does not require additional masks to generate the strap, results in a self-aligned strap and improved device performance. In one embodiment, the strap is a silicide strap.

摘要翻译： 公开了包括用于混合取向技术（HOT）衬底上的嵌入式沟槽存储器（例如，沟槽电容器）的自对准带的结构以及相关方法。 一种结构包括：包含绝缘体上半导体（SOI）部分和体半导体部分的混合取向衬底; SOI部分上的晶体管; 体半导体部分中的沟槽电容器; 以及从晶体管的源极/漏极区域延伸到沟槽电容器的电极的自对准带。 该方法不需要额外的掩模来生成带，导致自对准带和改进的设备性能。 在一个实施例中，带是硅化物带。

公开(公告)号：US07439559B2

公开(公告)日：2008-10-21

申请号：US11469039

申请日：2006-08-31

申请人： Kangguo Cheng ,  Ramachandra Divakaruni ,  Carl J. Radens

发明人： Kangguo Cheng ,  Ramachandra Divakaruni ,  Carl J. Radens

IPC分类号： H01L29/74

CPC分类号： H01L29/78642 ,  H01L27/10864 ,  H01L27/1087

摘要： A method of forming a memory cell having a trench capacitor and a vertical transistor in a semiconductor substrate includes a step of providing a bonded semiconductor wafer having a lower substrate with an [010] axis parallel to a first wafer axis and an upper semiconductor layer having an [010] axis oriented at forty-five degrees with respect to the wafer axis, the two being connected by a layer of bonding insulator; etching a trench through the upper layer and lower substrate; enlarging the lower portion of the trench and converting the cross section of the upper portion of the trench from octagonal to rectangular, so that sensitivity to alignment errors between the trench lithography and the active area lithography is reduced. An alternative version employs a bonded semiconductor wafer having a lower substrate formed from a (111) crystal structure and the same upper portion. Applications include a vertical transistor that becomes insensitive to misalignment between the trench and the lithographic pattern for the active area, in particular a DRAM cell with a vertical transistor.

摘要翻译： 在半导体衬底中形成具有沟槽电容器和垂直晶体管的存储单元的方法包括提供具有平行于第一晶片轴的[010]轴的下基板的接合半导体晶片的步骤，以及具有 相对于晶片轴线定向成四十五度的[010]轴，两者通过一层粘合绝缘体连接; 蚀刻通过上层和下衬底的沟槽; 扩大沟槽的下部并将沟槽的上部的横截面从八边形转换为矩形，从而降低对沟槽光刻和有源区光刻之间对准误差的敏感性。 替代方案采用具有由（111）晶体结构和相同上部形成的下基板的键合半导体晶片。 应用包括对于有源区域，特别是具有垂直晶体管的DRAM单元对沟槽和光刻图案之间的未对准变得不敏感的垂直晶体管。