公开(公告)号：US20070168937A1

公开(公告)日：2007-07-19

申请号：US11604716

申请日：2006-11-28

申请人： Soummya Mallick

发明人： Soummya Mallick

IPC分类号： G06F9/44 ,  G06F9/45

CPC分类号： G06F9/44584

摘要： An apparatus and method of application virtualization is disclosed. In one embodiment, a method includes automatically generating a virtual execution environment of an application-enabled drive, installing the virtual execution environment in user mode on a host system when the application-drive is electrically coupled to the host system, detecting any changes made to an operating system of the host system, and moving the virtual execution environment from the host system to the application-enabled drive when the application-enabled drive is electrically decoupled from the host system. A plurality of systems file modification of a host system may be detected due to an application installation. The plurality of systems file modification of the host system may be made by the application installation in the virtual execution environment. The plurality of systems file modification of the host system may be deleted when the application-enabled drive is electrically decoupled from the host system.

摘要翻译： 公开了一种应用虚拟化的装置和方法。 在一个实施例中，一种方法包括自动生成启用应用程序的驱动器的虚拟执行环境，当应用程序驱动器电耦合到主机系统时，将主机系统上的虚拟执行环境安装在主机系统上，检测对主机系统 主机系统的操作系统，并且当启用应用的驱动器与主机系统电分离时，将虚拟执行环境从主机系统移动到启用应用的驱动器。 由于应用安装，可能会检测到主机系统的多个系统文件修改。 可以通过虚拟执行环境中的应用安装来进行主机系统的多个系统文件修改。 当启用应用的驱动器与主机系统电分离时，可以删除主机系统的多个系统文件修改。

公开(公告)号：US20070094439A1

公开(公告)日：2007-04-26

申请号：US11254353

申请日：2005-10-20

申请人： Santosh Kumar ,  Soummya Mallick

发明人： Santosh Kumar ,  Soummya Mallick

IPC分类号： G06F12/00

CPC分类号： G06F9/4401 ,  G06F3/0616 ,  G06F3/0679

摘要： Apparatuses and methods of an expandable portable solid-state device are disclosed. In one embodiment, a solid-state device includes an expansion canister to enable coupling of a flash memory of the solid-state device to an external storage memory, and an executable-in-place module of the solid state device coupled to the flash memory to process a swap data to minimize a number of write operations in the flash memory. The executable-in-place module may include a secondary flash memory coupled to a dynamic random access memory. The dynamic random access memory may store at least as much data as the secondary flash memory. A logic circuit coupled to the secondary flash memory and the dynamic random access memory may copy data from the secondary flash memory to the dynamic random access memory on power up of a data processing system coupled to the solid-state device.

摘要翻译： 公开了可扩展便携式固态设备的装置和方法。 在一个实施例中，固态设备包括扩展罐，用于使固态设备的闪速存储器与外部存储存储器耦合，以及耦合到闪存的固态设备的可执行就绪模块 以处理交换数据以最小化闪存中的写入操作的数量。 可执行就地模块可以包括耦合到动态随机存取存储器的次闪存。 动态随机存取存储器可以存储与次闪存一样多的数据。 耦合到次闪存和动态随机存取存储器的逻辑电路可以在耦合到固态器件的数据处理系统的上电时将数据从次闪存存储器复制到动态随机存取存储器。

公开(公告)号：US5953520A

公开(公告)日：1999-09-14

申请号：US934645

申请日：1997-09-22

申请人： Soummya Mallick

发明人： Soummya Mallick

IPC分类号： G06F9/455

CPC分类号： G06F9/45504

摘要： A processor and method of operating a processor which has a native instruction set and emulates instructions in a guest instruction set are described. According to the method, a series of guest instructions from the guest instruction set are stored in memory. The series includes a guest memory access instruction that indicates a guest logical address in guest address space. For each guest instruction in the series, a semantic routine of native instructions from the native instruction set is stored in memory. The semantic routines, which utilize native addresses in native address space, can be executed in order to emulate the guest instructions. In response to receipt of the guest memory access instruction for emulation, the guest logical address is translated into a guest real address, which is thereafter translated into a native physical address. A semantic routine that emulates the guest memory access instruction is then executed utilizing the native physical address.

摘要翻译： 描述了一种处理器和操作处理器的方法，所述处理器具有本地指令集并且仿真访客指令集中的指令。 根据该方法，来自客户指令集的一系列访客指令被存储在存储器中。 该系列包括客户机存储器访问指令，其指示来宾地址空间中的来宾逻辑地址。 对于系列中的每个访客指令，本地指令集的本机指令的语义例程都存储在存储器中。 可以执行使用本地地址空间中的本地地址的语义例程，以便模拟客户指令。 响应于接收到用于仿真的访客存储器访问指令，客户逻辑地址被转换成客人实际地址，其后被翻译成本地物理地址。 然后，使用本地物理地址来执行模拟访客存储器访问指令的语义程序。

公开(公告)号：US5913054A

公开(公告)日：1999-06-15

申请号：US768059

申请日：1996-12-16

申请人： Soummya Mallick ,  Rajesh Bhikubhai Patel ,  Albert John Loper ,  Romesh Mangho Jessani

发明人： Soummya Mallick ,  Rajesh Bhikubhai Patel ,  Albert John Loper ,  Romesh Mangho Jessani

IPC分类号： G06F9/38 ,  G06F9/30 ,  G06F9/312 ,  G06F9/00

CPC分类号： G06F9/30043 ,  G06F9/3816 ,  G06F9/3824

摘要： A processor and method of processing a multiple-register instruction are described. The processor includes execution circuitry and a set of registers, which are each capable of storing a data word. A multiple-register instruction specifying a plurality of data words that are to be written to a corresponding plurality of registers within the set of registers is dispatched to the execution circuitry. In response to receipt of the multiple-register instruction, the execution circuitry executes the multiple-register instruction, such that at least two data words among the plurality of data words are written to at least two corresponding registers among the plurality of registers during a single cycle of the processor.

摘要翻译： 描述处理多寄存器指令的处理器和方法。 处理器包括执行电路和一组寄存器，它们都能够存储数据字。 指定要写入寄存器组内的相应多个寄存器的多个数据字的多寄存器指令被发送到执行电路。 响应于接收到多寄存器指令，执行电路执行多寄存器指令，使得在单个寄存器指令期间，多个数据字中的至少两个数据字被写入多个寄存器中的至少两个对应的寄存器 处理器的周期。

公开(公告)号：US5870577A

公开(公告)日：1999-02-09

申请号：US758066

申请日：1996-11-27

申请人： Rajesh B. Patel ,  Soummya Mallick ,  Romesh Mangho Jessani

发明人： Rajesh B. Patel ,  Soummya Mallick ,  Romesh Mangho Jessani

IPC分类号： G06F9/38

CPC分类号： G06F9/30167 ,  G06F9/3836 ,  G06F9/384 ,  G06F9/3853 ,  G06F9/3857

摘要： When the instruction dispatch unit detects two consecutive immediate instructions in the instruction queue directed to the same execution unit, it dispatches both during the same cycle, making use of both GPR ports for the two required GPR operands. Instruction path directing logic directs the first instruction to the execution decoder of the one execution unit during the first occurring cycle and latches the second instruction until a second occurring cycle. It also directs the first immediate operand of the first instruction to a first input of an execution block in the one execution unit during the first occurring cycle. An operand path directing logic directs the first GPR operand referred to by the first instruction to a second input of the execution block during the first occurring cycle and latches a second GPR operand referred to by the second instruction until the second occurring cycle. The instruction path directing logic directs the second instruction to the execution decoder during the second occurring cycle and directs the second immediate operand of the second instruction to the first input of the execution block during the second occurring cycle. The operand path directing logic directs the second GPR operand to the second input of the execution block during the second occurring cycle. In this manner, two instructions are dispatched in a single cycle from the instruction queue to one execution unit of the multiple execution unit parallel computer.

摘要翻译： 当指令调度单元检测到指向同一个执行单元的指令队列中的两个连续的立即指令时，它将在相同的周期内调度两个GPR端口两个所需的GPR操作数。 指令路径指令逻辑在第一次出现周期期间将第一指令指向一个执行单元的执行解码器，并将第二指令锁存到第二个发生周期。 它还在第一个发生周期中将第一指令的第一个立即操作数定向到一个执行单元中执行块的第一个输入。 操作数路径指令逻辑将第一指令引用的第一GPR操作数引导到执行块的第二个输入，并锁存第二指令引用的第二个GPR操作数直到第二个发生周期。 指令路径指令逻辑在第二发生周期期间将第二指令指引到执行解码器，并且在第二发生周期期间将第二指令的第二立即操作数引导到执行块的第一输入。 操作数路径定向逻辑在第二次发生周期期间将第二GPR操作数引导到执行块的第二个输入。 以这种方式，从指令队列到多个执行单元并行计算机的一个执行单元的单个周期中分派两个指令。

公开(公告)号：US5812823A

公开(公告)日：1998-09-22

申请号：US581794

申请日：1996-01-02

申请人： James Allan Kahle ,  Soummya Mallick ,  Arturo Martin-de-Nicolas

发明人： James Allan Kahle ,  Soummya Mallick ,  Arturo Martin-de-Nicolas

IPC分类号： G06F9/30 ,  G06F9/455 ,  G06F9/46 ,  G06F9/48

CPC分类号： G06F9/3879 ,  G06F9/30101 ,  G06F9/30112 ,  G06F9/30123 ,  G06F9/3013 ,  G06F9/30174 ,  G06F9/45533 ,  G06F9/461

摘要： A system and method for performing an emulation context switch save and restore in a processor that executes host applications and emulates guest applications. The processor includes an operating system and a first register that is saved and restored by the operating system during a host application context switch. The method and system comprises renaming the special-purpose register to the first register when emulating guest applications. When an emulation context switch occurs, a context save and restore of the special-purpose register is performed through the first register without operating system modification.

摘要翻译： 用于执行仿真上下文切换的系统和方法在执行主机应用并且模拟来宾应用的处理器中保存和恢复。 处理器包括操作系统和在主机应用程序上下文切换期间由操作系统保存和恢复的第一寄存器。 该方法和系统包括在模拟客户应用程序时将专用寄存器重命名为第一寄存器。 当发生仿真上下文切换时，通过第一个寄存器执行专用寄存器的上下文保存和恢复，无需操作系统修改。

公开(公告)号：US5802556A

公开(公告)日：1998-09-01

申请号：US680808

申请日：1996-07-16

申请人： Rajesh Bhikhubhai Patel ,  Soummya Mallick

发明人： Rajesh Bhikhubhai Patel ,  Soummya Mallick

IPC分类号： G06F9/315 ,  G06F9/312 ,  G06F9/38 ,  G06F12/04

CPC分类号： G06F9/30043 ,  G06F9/3816 ,  G06F9/3824 ,  G06F9/3836 ,  G06F9/384 ,  G06F9/3855 ,  G06F9/3857

摘要： In a microprocessor having a plurality of execution units, rename register, architectural registers, and a cache for storing blocks of data, each block having a plurality of words, a method for aligning bytes stored in separate words. In one version, the method includes the steps of reading a first word of data from the cache; rotating the first word to align a first byte with respect to a first byte of a rename register; storing the first aligned byte in the rename register; reading a second word from the cache; rotating the second word to align a second byte with respect to a second byte of the rename register; and storing the second aligned byte in the rename register.

摘要翻译： 在具有多个执行单元的微处理器中，重命名寄存器，结构寄存器和用于存储数据块的高速缓冲存储器，每个块具有多个字，用于对准以单独字形存储的字节。 在一个版本中，该方法包括从缓存读取数据的第一个字的步骤; 旋转第一个字以使第一个字节相对于重命名寄存器的第一个字节对齐; 将第一对齐字节存储在重命名寄存器中; 从缓存读取第二个字; 旋转所述第二字以使第二字节相对于所述重命名寄存器的第二字节对齐; 并将第二对齐字节存储在重命名寄存器中。

公开(公告)号：US5754811A

公开(公告)日：1998-05-19

申请号：US730606

申请日：1996-10-08

申请人： Michael Putrino ,  Soummya Mallick ,  Albert John Loper

发明人： Michael Putrino ,  Soummya Mallick ,  Albert John Loper

IPC分类号： G06F5/10 ,  G06F9/38 ,  G06F9/00

CPC分类号： G06F5/10 ,  G06F9/3802 ,  G06F9/3814

摘要： A circular dispatch queue is used to implement an instruction queue, in a microprocessor, in order to reduce the delay associated with the critical timing path between an instruction cache memory and the instruction queue. In the circular dispatch queue, instructions are never moved from one stage to another. Instead, pointers are maintained that indicate the top and bottom instructions within the circular dispatch queue. This technique removes inputs from the multiplexor between the register stages in the circular dispatch queue and the instruction cache memory, thus reducing the critical delay.

摘要翻译： 循环调度队列用于在微处理器中实现指令队列，以便减少与指令高速缓冲存储器和指令队列之间的关键定时路径相关联的延迟。 在循环调度队列中，指令不会从一个阶段移动到另一个阶段。 相反，维护指示循环调度队列中的顶部和底部指令的指针。 该技术从循环调度队列中的寄存器阶段和指令高速缓冲存储器之间的多路复用器消除输入，从而减少临界延迟。

公开(公告)号：US5995743A

公开(公告)日：1999-11-30

申请号：US935007

申请日：1997-09-22

申请人： James Allan Kahle ,  Soummya Mallick

发明人： James Allan Kahle ,  Soummya Mallick

IPC分类号： G06F9/318 ,  G06F9/38 ,  G06F9/455 ,  G06F9/48 ,  G06F9/44

CPC分类号： G06F9/4812 ,  G06F9/30174 ,  G06F9/3861 ,  G06F9/45554

摘要： A processor and method of interrupt handling in a processor which has a native instruction set and emulates guest instructions within a guest instruction set are described. According to the method, in response to occurrence of an interrupt during emulation of a current guest instruction, an indication of a location in memory of the current guest instruction, an indication of a location in memory of a next guest instruction to be emulated, and an indication of a particular native instruction are stored. After an interrupt handler is executed, emulation is resumed by executing native instructions beginning with the particular native instruction. In response to execution of a native instruction of a first type before execution of a native instruction of a second type, the current guest instruction is fetched from memory. In response to execution of a native instruction of the second type before execution of a native instruction of the first type, the next guest instruction is fetched from memory without fetching the current guest instruction.

摘要翻译： 描述了处理器中的处理器和方法，该处理器具有本地指令集并且模拟客户指令集中的访客指令。 根据该方法，响应于在当前客户指令的仿真期间发生中断，当前客户指令的存储器中的位置的指示，要被仿真的下一个客户指令的存储器中的位置的指示，以及 存储特定本机指令的指示。 执行中断处理程序后，通过以特定的本机指令开始执行本地指令来恢复仿真。 响应于在执行第二类型的本机指令之前执行第一类型的本机指令，从存储器中取出当前的客户指令。 响应于在执行第一类型的本机指令之前执行第二类型的本地指令，从存储器中取出下一个访客指令而不取得当前的客户指令。

公开(公告)号：US5870616A

公开(公告)日：1999-02-09

申请号：US726871

申请日：1996-10-04

申请人： Albert John Loper ,  Soummya Mallick

发明人： Albert John Loper ,  Soummya Mallick

IPC分类号： G06F1/26 ,  G06F1/32 ,  G06F9/38 ,  G06F12/08 ,  G06F15/78 ,  G11C7/00

CPC分类号： G06F9/3802 ,  G06F1/32 ,  G06F1/3275 ,  G06F12/0864 ,  G06F9/3824 ,  G06F9/3836 ,  G06F9/384 ,  G06F9/3855 ,  G06F9/3857 ,  G06F9/3869 ,  G06F2212/1028 ,  Y02B60/1225 ,  Y02B60/1228

摘要： While a set-associative cache memory operates in a first power mode, information is stored in up to N number of ways of the cache memory, where N is an integer number and N>1. While the cache memory operates in a second power mode, the information is stored in up to M number of ways of the cache memory, where M is an integer number and 0

摘要翻译： 虽然集合关联高速缓存存储器以第一功率模式运行，但信息以高达N个数量的高速缓冲存储器的方式存储，其中N是整数，N> 1。 当高速缓冲存储器以第二功率模式工作时，该信息以高达M个数量的高速缓冲存储器的方式被存储，其中M是整数，0